IS61LV12824 ISSI 128K x 24 HIGH-SPEED CMOS STATIC RAM JUNE 2005 WITH 3.3V SUPPLY FEATURES DESCRIPTION The ISSI IS61LV12824 is a high-speed, static RAM organized High-speed access time: 8, 10 ns as 131,072 words by 24 bits. It is fabricated using ISSI s high- CMOS low power operation performance CMOS technology. This highly reliable process 756 mW (max.) operating 8 ns coupled with innovative circuit design techniques, yields ac- cess times as fast as 8 ns with low power consumption. 36 mW (max.) standby 8 ns TTL compatible interface levels When CE1, CE2 are HIGH and CE2 is LOW (deselected), the Single 3.3V power supply device assumes a standby mode at which the power dissipa- tion can be reduced down with CMOS input levels. Fully static operation: no clock or refresh required Easy memory expansion is provided by using Chip Enable Three state outputs and Output Enable inputs, CE1, CE2, CE2 and OE. The active Available in 119-pin Plastic Ball Grid Array LOW Write Enable (WE) controls both writing and reading of (PBGA) and 100-pin TQFP packages. the memory. Industrial temperature available The IS61LV12824 is packaged in the JEDEC standard Lead-free available 119-pin PBGA and 100-pin TQFP. FUNCTIONAL BLOCK DIAGRAM 128K x 24 A0-A16 DECODER MEMORY ARRAY VCC GND I/O COLUMN I/O DATA I/O0-I/O23 CIRCUIT CE2 CE1 CONTROL CE2 CIRCUIT OE WE Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. D 06/22/05 ISSI IS61LV12824 PIN CONFIGURATION - 119-pin PBGA PIN DESCRIPTIONS 1234567 A0-A16 Address Inputs A NC A11 A14 A15 A16 A4 NC I/O0-I/O23 Data Inputs/Outputs B NC A12 A13 CE1 A5 A3 NC CE1, CE2 Chip Enable Input LOW C I/O16 NC CE2 NC CE2 NC I/O0 CE2 Chip Enable Input HIGH D I/O17 VCCQ GND GND GND VCCQ I/O1 OE Output Enable Input E I/O18 GND VCC GND VCC GND I/O2 WE Write Enable Input F I/O19 VCCQ GND GND GND VCCQ I/O3 NC No Connection G I/O20 GND VCC GND VCC GND I/O4 Vcc Power H I/O21 VCCQ GND GND GND VCCQ I/O5 VCCQ I/O Power J VCCQ GND VCC GND VCC GND VCCQ GND Ground K I/O22 VCCQ GND GND GND VCCQ I/O6 L I/O23 GND VCC GND VCC GND I/O7 M I/O12 VCCQ GND GND GND VCCQ I/O8 N I/O13 GND VCC GND VCC GND I/O9 P I/O14 VCCQ GND GND GND VCCQ I/O10 R I/O15 NC NC NC NC NC I/O11 T NC A10 A8 WE A0 A1 NC U NC A9 A7 OE A6 A2 NC 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. D 06/22/05