IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A 1Mx36and2Mx18 36Mb,FLOW THROUGH NO WAIT FEBRUARY2012 STATEBUSSRAM DESCRIPTION FEATURES The 36 Meg NLF/NVF product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read andWr ite a burstable, high-performance, no wait state, device for networking and communications applications. They are Internal self-timed write cycle organized as 1M words by 36 bits and 2M words by 18 Individual ByteWr ite Control bits, fabricated withISSI s advanced CMOS technology. Single Read/Write control pin Incorporating a no wait state feature, wait cycles are Clock controlled, registered address, eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, data and control high-speed SRAM core, and high-drive capability outputs Interleaved or linear burst sequence control us- into a single monolithic circuit. ing MODE input All synchronous inputs pass through registers are controlled Three chip enables for simple depth expansion by a positive-edge-triggered single clock input. Operations and address pipelining may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal Power Down mode device will hold their previous values. Common data inputs and data outputs All Read, Write and Deselect cycles are initiated by the ADV CKE pin to enable clock and suspend operation input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded JEDEC 100-pinTQFP package when ADV is LOW. Power supply: Write cycles are internally self-timed and are initiated NVF: Vdd 2.5V ( 5%),V ddq 2.5V ( 5%) by the rising edge of the clock inputs and when WE is NLF: Vdd 3.3V ( 5%),V ddq 3.3V/2.5V ( 5%) LOW. Separate byte enables allow individual bytes to be Industrial temperature available written. Lead-free available A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FASTACCESS TIME Symbol Parameter 6.5 7.5 Units tkq Clock Access Time 6.5 7.5 ns tkc Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without ISSInotice assumes. no liability arising out of the application or use of any information, products or services described herein.Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness Products. are not authorized for use in such applications unless Integrated Silicon Solution, receiv Inc.es written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. C 02/12/2012IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A BLOCKDIAGRAM A2-A19 or A2-A20 x 36: A 0:19 or 1Mx36 ADDRESS x 18: A 0:20 2Mx18 REGISTER MEMORY ARRAY MODE BURST ADDRESS DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER WRITE CLK CONTROL ADDRESS LOGIC CKE REGISTER CE CE2 CE2 CONTROL ADV REGISTER CONTROL WE LOGIC BWX (X=a-d, or a,b) BUFFER OE ZZ 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. C 02/02/2012