IS61(4)NLF12836EC/IS61(4)NVF12836EC/IS61(4)NLF12832EC IS61(4)NVF12832EC/IS61(4)NLF25618EC/IS61(4)NVF25618EC 128K x36/32 and 256K x18 4Mb, ECC, FLOW THROUGH NO WAIT STATE BUS SYNCHRONOUS SRAM APRIL 2017 FEATURES DESCRIPTION 100 percent bus utilization The 4Mb product family features high-speed, low- power synchronous static RAMs designed to No wait cycles between Read and Write provide a burstable, high-performance, no wait Internal self-timed write cycle state, device for networking and communications Individual Byte Write Control applications. They are organized as 128K words Single R/W (Read/Write) control pin by 36 bits and 256K words by 18 bits, fabricated Clock controlled, registered address, data and with ISSI s advanced CMOS technology. control Incorporating a no wait state feature, wait cycles are eliminated when the bus switches from read Interleaved or linear burst sequence control to write, or write to read. This device integrates a using MODE input 2-bit burst counter, high-speed SRAM core, and Three chip enables for simple depth high-drive capability outputs into a single expansion and address pipelining monolithic circuit. Power Down mode All synchronous inputs pass through registers are Common data inputs and data outputs controlled by a positive-edge-triggered single /CKE pin to enable clock and suspend clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, operation /CKE is HIGH. In this state the internal device will JEDEC 100-pin QFP, 165-ball BGA and 119- hold their previous values. ball BGA packages All Read, Write and Deselect cycles are initiated Power supply: by the ADV input. When the ADV is HIGH the NLF: V 3.3V ( 5%), V 3.3V/2.5V ( 5%) DD DDQ internal burst counter is incremented. New NVF: VDD 2.5V ( 5%), VDDQ 2.5V ( 5%) external addresses can be loaded when ADV is JTAG Boundary Scan for BGA packages LOW. Write cycles are internally self-timed and are Industrial and Automotive temperature support initiated by the rising edge of the clock inputs and Lead-free available when /WE is LOW. Separate byte enables allow Error Detection and Error Correction individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter -6.5 -7.5 Units tKQ Clock Access Time 6.5 7.5 ns tKC Cycle time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. C2 04/21/2017 IS61(4)NLF12836EC/IS61(4)NVF12836EC/IS61(4)NLF12832EC IS61(4)NVF12832EC/IS61(4)NLF25618EC/IS61(4)NVF25618EC BLOCK DIAGRAM Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. C2 04/21/2017