IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A 128Kx 36and256K x18 4Mb,FLOW THROUGH NO WAIT AUGUST2011 STATEBUSSRAM FEATURES DESCRIPTION The 4 Meg NLF/NVF product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Write a burstable, high-performance, no wait state, device for Internal self-timed write cycle networking and communications applications. They are organized as 128K words by 36 bits and 256K words by Individual Byte Write Control 18 bits, fabricated with ISSI s advanced CMOS technology. Single Read/Write control pin Incorporating a no wait state feature, wait cycles are Clock controlled, registered address, eliminated when the bus switches from read to write, or data and control write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs Interleaved or linear burst sequence control us- into a single monolithic circuit. ing MODE input All synchronous inputs pass through registers are controlled Three chip enables for simple depth expansion by a positive-edge-triggered single clock input. Operations and address pipelining may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal Power Down mode device will hold their previous values. Common data inputs and data outputs All Read, Write and Deselect cycles are initiated by the ADV CKE pin to enable clock and suspend operation input. When the ADV is HIGH the internal burst counter JEDEC 100-pin TQFP, 119-ball PBGA, and 165- is incremented. New external addresses can be loaded when ADV is LOW. ball PBGA packages Write cycles are internally self-timed and are initiated by Power supply: the rising edge of the clock inputs and when WE is LOW. NVF: Vdd 2.5V ( 5%), Vddq 2.5V ( 5%) Separate byte enables allow individual bytes to be written. NLF: Vdd 3.3V ( 5%), Vddq 3.3V/2.5V ( 5%) A burst mode pin (MODE) defines the order of the burst Industrial temperature available sequence. When tied HIGH, the interleaved burst sequence Lead-free available is selected. When tied LOW, the linear burst sequence is selected. FASTA CCESS TIME Symbol Parameter 6.5 7.5 Units tkq Clock Access Time 6.5 7.5 ns tkc Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. D 08/11/2011 IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A BLOCKDIA GRAM A2-A16 or A2-A17 128Kx36 ADDRESS x 36: A 0:16 or 256Kx18 REGISTER x 18: A 0:17 MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL WE LOGIC BWX (X= a-d, or a,b) BUFFER OE ZZ 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com Rev. D 08/11/2011