IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 NOVEMBER 2013 256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH NO WAIT STATE BUS SRAM FEATURES DESCRIPTION The 18 Meg NLF/NVF product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Wr ite a burstable, high-perfor mance, no wait state, device Inter nal self-timed wr ite cycle for networ king and communications applications. They are organized as 256K words by 72 bits, 512K words Individual Byte Wr ite Control by 36 bits and 1M words by 18 bits, fabr icated with ISSI s Single Read/Wr ite control pin advanced CMOS technology. Clock controlled, registered address, Incor porating a no wait state feature, wait cycles are data and control eliminated when the bus switches from read to write, or wr ite to read. This device integrates a 2-bit burst counter, Inter leaved or linear burst sequence control us- high-speed SRAM core, and high-dr ive capability outputs ing MODE input into a single monolithic circuit. Three chip enables for simple depth expansion All synchronous inputs pass through registers are controlled and address pipelining by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored Power Down mode when Clock Enable, CKE is HIGH. In this state the inter nal Common data inputs and data outputs device will hold their previous values. CKE pin to enable clock and suspend operation All Read, Wr ite and Deselect cycles are initiated by the ADV JEDEC 100-pin TQFP, 165-ball PBGA and 209- input. When the ADV is HIGH the inter nal burst counter is incremented. New exter nal addresses can be loaded ball (x72) PBGA packages when ADV is LOW. Power supply: Wr ite cycles are inter nally self-timed and are initiated by NVF: Vdd 2.5V ( 5%), Vddq 2.5V ( 5%) the rising edge of the clock inputs and when WE is LOW. NLF: Vdd 3.3V ( 5%), Vddq 3.3V/2.5V ( 5%) Separate byte enables allow individual bytes to be written. JTAG Boundar y Scan for PBGA packages A burst mode pin (MODE) defines the order of the burst Industr ial temperature available sequence. When tied HIGH, the inter leaved burst sequence is selected. When tied LOW, the linear burst sequence is Lead-free available selected. FAST ACCESS TIME Symbol Parameter 6.5 7.5 Units tkq Clock Access Time 6.5 7.5 ns tkc Cycle Time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil- ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. E 10/25/2013IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236 IS61NLF102418/IS61NVF102418 BLOCK DIAGRAM x 72: A 0:17 or A2-A17 or A2-A18 or A2-A19 256Kx72 512Kx36 x 36: A 0:18 or ADDRESS 1024Kx18 x 18: A 0:19 REGISTER MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL WE LOGIC BWX (X=a-h, a-d, or a,b) BUFFER OE ZZ 72, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. E 10/25/2013