IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC 128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM APRIL 2017 FEATURES DESCRIPTION 100 percent bus utilization The 4Mb product family features high-speed, low- power synchronous static RAMs designed to No wait cycles between Read and Write provide a burstable, high-performance, no wait Internal self-timed write cycle state, device for networking and communications Individual Byte Write Control applications. They are organized as 128K words Single R/W (Read/Write) control pin by 36 bits and 256K words by 18 bits, fabricated with ISSI s advanced CMOS technology. Clock controlled, registered address, data and Incorporating a no wait state feature, wait cycles control are eliminated when the bus switches from read Interleaved or linear burst sequence control to write, or write to read. This device integrates a using MODE input 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single Three chip enables for simple depth monolithic circuit. expansion and address pipelining All synchronous inputs pass through registers are Power Down mode controlled by a positive-edge-triggered single Common data inputs and data outputs clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, /CKE pin to enable clock and suspend /CKE is HIGH. In this state the internal device will operation hold their previous values. JEDEC 100-pin QFP, 165-ball BGA and 119- All Read, Write and Deselect cycles are initiated ball BGA packages by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New Power supply: external addresses can be loaded when ADV is NLP: V 3.3V ( 5%), V 3.3V/2.5V ( 5%) DD DDQ LOW. NVP: VDD 2.5V ( 5%), VDDQ 2.5V ( 5%) Write cycles are internally self-timed and are JTAG Boundary Scan for BGA packages initiated by the rising edge of the clock inputs and when /WE is LOW. Separate byte enables allow Industrial and Automotive temperature support individual bytes to be written. Lead-free available A burst mode pin (MODE) defines the order of the Error Detection and Error Correction burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected FAST ACCESS TIME Symbol Parameter 250 200 Units tKQ Clock Access Time 2.6 3.1 ns tKC Cycle time 4 5 ns fMAX Frequency 250 200 MHz Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. D2 04/21/2017 IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC BLOCK DIAGRAM Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. D2 04/21/2017