IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 AUGUST 2014 9Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES DESCRIPTION The 9 Meg NLP/NVP product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Wr ite a burstable, high-perfor mance, no wait state, device for Inter nal self-timed wr ite cycle networ king and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 Individual Byte Wr ite Control bits, fabricated with ISSI s advanced CMOS technology. Single R/W (Read/Wr ite) control pin Incor porating a no wait state feature, wait cycles are Clock controlled, registered address, eliminated when the bus switches from read to write, or data and control wr ite to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-dr ive capability outputs Inter leaved or linear burst sequence control us- into a single monolithic circuit. ing MODE input All synchronous inputs pass through registers are controlled Three chip enables for simple depth expansion by a positive-edge-tr iggered single clock input. Operations and address pipelining may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the inter nal Power Down mode device will hold their previous values. Common data inputs and data outputs All Read, Wr ite and Deselect cycles are initiated by the ADV CKE pin to enable clock and suspend operation input. When the ADV is HIGH the inter nal burst counter JEDEC 100-pin TQFP, 165-ball PBGA and is incremented. New exter nal addresses can be loaded when ADV is LOW. 119-ball PBGA packages Wr ite cycles are inter nally self-timed and are initiated Power supply: by the rising edge of the clock inputs and when WE is NVP: Vdd 2.5V ( 5%), Vddq 2.5V ( 5%) LOW. Separate byte enables allow individual bytes to be NLP: Vdd 3.3V ( 5%), Vddq 3.3V/2.5V ( 5%) written. JTAG Boundar y Scan for PBGA packages A burst mode pin (MODE) defines the order of the burst Industr ial temperature available sequence. When tied HIGH, the inter leaved burst sequence is selected. When tied LOW, the linear burst sequence is Lead-free available selected. FAST ACCESS TIME Symbol Parameter -250 -200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. J 08/25/2014 IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A BLOCK DIAGRAM A2-A17 or A2-A18 256Kx36 x 36: A 0:17 or ADDRESS 512Kx18 x 18: A 0:18 REGISTER MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL OUTPUT WE LOGIC REGISTER BWX (X=a,b,c,d or a,b) BUFFER OE ZZ 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. J 08/25/2014