Long-term Support IS61NLP25636B/IS61NVP/NVVP25636B World Class Quality IS61NLP51218B/IS61NVP/NVVP51218B 256K x 36 and 512K x 18 JUNE 2017 9Mb, PIPELINE NO WAIT STATE BUS SRAM FEATURES DESCRIPTION The 9 Meg product family features high-speed, low-power 100 percent bus utilization synchronous static RAMs designed to provide a burstable, No wait cycles between Read and Write high-performance, no wait state, device for networking and Internal self-timed write cycle communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated Individual Byte Write Control with ISSI s advanced CMOS technology. Single R/W (Read/Write) control pin Incorporating a no wait state feature, wait cycles are Clock controlled, registered address, eliminated when the bus switches from read to write, or data and control write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs Interleaved or linear burst sequence control us- into a single monolithic circuit. ing MODE input All synchronous inputs pass through registers are controlled Three chip enables for simple depth expansion by a positive-edge-triggered single clock input. Operations and address pipelining may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal Power Down mode device will hold their previous values. Common data inputs and data outputs All Read, Write and Deselect cycles are initiated by the ADV CKE pin to enable clock and suspend operation input. When the ADV is HIGH the internal burst counter JEDEC 100-pin QFP, 165-ball BGA and 119-ball is incremented. New external addresses can be loaded when ADV is LOW. BGA packages Write cycles are internally self-timed and are initiated Power supply: by the rising edge of the clock inputs and when WE is NLP: Vdd 3.3V ( 5%), Vddq 3.3V/2.5V ( 5%) LOW. Separate byte enables allow individual bytes to be NVP: Vdd 2.5V ( 5%), Vddq 2.5V ( 5%) written. NVVP: Vdd 1.8V ( 5%), Vddq 1.8V ( 5%) A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence JTAG Boundary Scan for BGA packages is selected. When tied LOW, the linear burst sequence is Industrial temperature available selected. Lead-free available FAST ACCESS TIME Symbol Parameter -250 -200 -166 Units tkq Clock Access Time 2.6 3.1 3.5 ns tkc Cycle Time 4 5 6 ns Frequency 250 200 166 MHz Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. A3 06/21/2017 Long-term Support IS61NLP25636B/IS61NVP/NVVP25636B World Class Quality IS61NLP51218B/IS61NVP/NVVP51218B BLOCK DIAGRAM A0-17 ( A0-18) A0-17 ( A0-18) A2-17(A2-A18) A0-17(A0-18) Address MODE 256Kx36 Registers 512Kx18 Burst Logic ADV Memory Array A0-A1 A 0-A 1 K K Address Address CLK Registers Registers /CKE Data-In Register K /CE CE2 /CE2 Data-In Register Control Logic ADV K /WE /BWx (X=a,b,c,d or a,b) /OE Output Output ZZ Buffers Register K 36(18) K DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. A3 06/21/2017 Control register