IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 256Kx72, 512Kx36and1Mx18 18Mb,PIPELINE NO WAIT STATEB USSRAM SEPTEMBER2011 FEATURES DESCRIPTION The 18 Meg NLP/NVP product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Write a burstable, high-performance, no wait state, device Internal self-timed write cycle for networking and communications applications. They are organized as 256K words by 72 bits, 512K words Individual Byte Write Control by 36 bits and 1M words by 18 bits, fabricated with ISSI s Single R/W (Read/Write) control pin advanced CMOS technology. Clock controlled, registered address, Incorporating a no wait state feature, wait cycles are data and control eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, Interleaved or linear burst sequence control us- high-speed SRAM core, and high-drive capability outputs ing MODE input into a single monolithic circuit. Three chip enables for simple depth expansion All synchronous inputs pass through registers are controlled and address pipelining by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored Power Down mode when Clock Enable, CKE is HIGH. In this state the internal Common data inputs and data outputs device will hold their previous values. CKE pin to enable clock and suspend operation All Read, Write and Deselect cycles are initiated by the ADV JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded PBGA and 209-ball (x72) PBGA packages when ADV is LOW. Power supply: Write cycles are internally self-timed and are initiated by NVP: Vdd 2.5V ( 5%), Vddq 2.5V ( 5%) the rising edge of the clock inputs and when WE is LOW. NLP: Vdd 3.3V ( 5%), Vddq 3.3V/2.5V ( 5%) Separate byte enables allow individual bytes to be written. JTAG Boundary Scan for PBGA packages A burst mode pin (MODE) defines the order of the burst Industrial temperature available sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is Lead-free available selected. Leaded option available upon request FASTA CCESS TIME Symbol Parameter -250 -200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. O 09/19/2011IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 BLOCKDIA GRAM x 72: A 0:17 or A2-A17 or A2-A18 or A2-A19 256Kx72 512Kx36 x 36: A 0:18 or ADDRESS 1024Kx18 x 18: A 0:19 REGISTER MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL OUTPUT WE LOGIC REGISTER BWX (X=a,b,c,d or a,b) BUFFER OE ZZ 72, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com Rev.O 09/19/2011