IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM AUGUST 2019 FEATURES DESCRIPTION 100 percent bus utilization The 18Meg product family features high-speed, low- power synchronous static RAMs designed to provide No wait cycles between Read and Write a burstable, high-performance, no wait state, Internal self-timed write cycle device for networking and communications Individual Byte Write Control applications. They are organized as 512K words by Single R/W (Read/Write) control pin 36 bits and 1024K words by 18 bits, fabricated with Clock controlled, registered address, data and ISSI s advanced CMOS technology. control Incorporating a no wait state feature, wait cycles Interleaved or linear burst sequence control are eliminated when the bus switches from read to using MODE input write, or write to read. This device integrates a 2-bit Three chip enables for simple depth burst counter, high-speed SRAM core, and high- expansion and address pipelining drive capability outputs into a single monolithic Power Down mode circuit. Common data inputs and data outputs All synchronous inputs pass through registers are /CKE pin to enable clock and suspend controlled by a positive-edge-triggered single clock operation input. Operations may be suspended and all JEDEC 100-pin QFP, 165-ball BGA and 119- synchronous inputs ignored when Clock Enable, ball BGA packages /CKE is HIGH. In this state the internal device will Power supply: hold their previous values. NLP: V 3.3V ( 5%), V 3.3V/2.5V ( 5%) DD DDQ All Read, Write and Deselect cycles are initiated by NVP: V 2.5V ( 5%), V 2.5V ( 5%) the ADV input. When the ADV is HIGH the internal DD DDQ NVVP: V 1.8V ( 5%), V 1.8V ( 5%) burst counter is incremented. New external DD DDQ addresses can be loaded when ADV is LOW. JTAG Boundary Scan for BGA packages Write cycles are internally self-timed and are Commercial, Industrial and Automotive (x36) initiated by the rising edge of the clock inputs and temperature support when /WE is LOW. Separate byte enables allow Lead-free available individual bytes to be written. For leaded option, please contact ISSI. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter -250 -200 Units tKQ Clock Access Time 2.6 3.0 ns tKC Cycle time 4 5 ns Frequency 250 200 MHz Copyright 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. D2 08/12/2019 IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B BLOCK DIAGRAM (X= a,b,c,d or Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. D2 08/12/2019