IS61NLF51236(32)B/IS61NVF51236(32)B/IS61NVVF51236(32)B IS61NLF102418B/IS61NVF102418B/IS61NVVF102418B 512K x36 and 1024K x18 18Mb, FLOW THROUGH NO WAIT STATE BUS SYNCHRONOUS SRAM JUNE 2015 FEATURES DESCRIPTION 100 percent bus utilization The 18Meg product family features high-speed, No wait cycles between Read and Write low-power synchronous static RAMs designed to Internal self-timed write cycle provide a burstable, high-performance, no wait Individual Byte Write Control state, device for networking and communications Single R/W (Read/Write) control pin applications. They are organized as 512K words Clock controlled, registered address, data and by 36 bits and 1024K words by 18 bits, fabricated control with ISSI s advanced CMOS technology. Interleaved or linear burst sequence control Incorporating a no wait state feature, wait cycles using MODE input are eliminated when the bus switches from read Three chip enables for simple depth to write, or write to read. This device integrates a expansion and address pipelining 2-bit burst counter, high-speed SRAM core, and Power Down mode high-drive capability outputs into a single Common data inputs and data outputs monolithic circuit. /CKE pin to enable clock and suspend All synchronous inputs pass through registers are operation controlled by a positive-edge-triggered single JEDEC 100-pin QFP, 165-ball BGA and 119- clock input. Operations may be suspended and all ball BGA packages synchronous inputs ignored when Clock Enable, Power supply: /CKE is HIGH. In this state the internal device will NLF: V 3.3V ( 5%), V 3.3V/2.5V ( 5%) hold their previous values. DD DDQ NVF: V 2.5V ( 5%), V 2.5V ( 5%) All Read, Write and Deselect cycles are initiated DD DDQ NVVF: V 1.8V ( 5%), V 1.8V ( 5%) by the ADV input. When the ADV is HIGH the DD DDQ JTAG Boundary Scan for BGA packages internal burst counter is incremented. New Commercial, Industrial and Automotive external addresses can be loaded when ADV is temperature support LOW. Lead-free available Write cycles are internally self-timed and are For leaded option, please contact ISSI. initiated by the rising edge of the clock inputs and when /WE is LOW. Separate byte enables allow individual bytes to be written. FAST ACCESS TIME A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the Symbol Parameter -6.5 -7.5 Units linear burst sequence is selected. Clock Access tKQ 6.5 7.5 ns Time tKC Cycle time 7.5 8.5 ns Frequency 133 117 MHz Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. D 05/27/2015 IS61NLF51236(32)B/IS61NVF51236(32)B/IS61NVVF51236(32)B IS61NLF102418B/IS61NVF102436B/IS61NVVF102418B BLOCK DIAGRAM (X = a, b, c,d Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. D 05/27/2015