. 36 Mb (1M x 36 & 2M x 18) I QUAD (Burst of 2) Synchronous SRAMs Two echo clocks (CQ and CQ) that are delivered Features simultaneously with data. 1M x 36 or 2M x 18. +1.8V core power supply and 1.5, 1.8V V , DDQ On-chip delay-locked loop (DLL) for wide data used with 0.75, 0.9V V . REF valid window. HSTL input and output levels. Separate read and write ports with concurrent Registered addresses, write and read controls, read and write operations. byte writes, data in, and data outputs. Synchronous pipeline read with early write oper- Full data coherency. ation. Boundary scan using limited set of JTAG 1149.1 Double data rate (DDR) interface for read and functions. write input ports. Byte write capability. Fixed 2-bit burst for read and write operations. Fine ball grid array (FBGA) package Clock stop support. - 15mm x 17mm body size Two input clocks (K and K) for address and con- - 1mm pitch trol registering at rising edges only. - 165-ball (11 x 15) array Two input clocks (C and C) for data output con- Programmable impedance output drivers via 5x trol. user-supplied precision resistor. Description The 36Mb IS61QDB21Mx36 and IS61QDB22Mx18 Write address are synchronous, high-performance CMOS static Byte writes random access memory (SRAM) devices. These Data-in for second burst addresses These SRAMs have separate I/Os, eliminating the Byte writes can change with the corresponding data- need for high-speed bus turnaround. The rising in to enable or disable writes on a per-byte basis. An edge of K clock initiates the read/write operation, internal write buffer enables the data-ins to be regis- and all internal operations are self-timed. Refer to tered half a cycle earlier than the write address. The the Timing Reference Diagram for Truth Table first data-in burst is clocked at the same time as the on page 8 for a description of the basic opera- write command signal, and the second burst is timed tions of these SRAMs. to the following rising edge of the K clock. The input address bus operates at double data rate. During the burst read operation, the data-outs from The following are registered internally on the rising the first burst are updated from output registers off edge of the K clock: the second rising edge of the C clock (1.5 cycles Read address later). The data-outs from the second burst are Read enable updated with the third rising edge of the C clock. The Write enable K and K clocks are used to time the data-outs when- Byte writes ever the C and C clocks are tied high. Data-in for early writes The device is operated with a single +1.8V power The following are registered on the rising edge of supply and is compatible with HSTL I/O interfaces. the K clock: Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. H 1/6/201036 Mb (1M x 36 & 2M x 18) I QUAD (Burst of 2) Synchronous SRAMs x36 FBGA Pinout (Top View) 12 34 56 78 9 10 11 V /SA NC/SA* W BW K BW R SA V /SA CQ ACQ SS 2 1 SS B Q27 Q18 D18 SA BW KBW SA D17 Q17 Q8 3 0 C D27 Q28 D19 V SA SA SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ HDoff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SASASA C SA SA SA TMS TDI Note: The following pins are reserved for higher densities: A3 for 64Mb, 10A for 144Mb, and 2A for 288Mb. x18 FBGA Pinout (Top View) 12 34 56 78 9 10 11 ACQ V /SA* SA W BW K NC R SA V /SA* CQ SS 1 SS BNC Q9 D9 SA NC K BW SA NC NC Q8 0 CNC NC D10 V SA SA SA V NC Q7 D8 SS SS DNC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS ENC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ FNC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ GNC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ HDoff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF JNC NC D14 V V V V V NC Q4 D4 DDQ DD SS DD DDQ KNC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ LNC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ MNC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS NNC D17 Q16 V SA SA SA V NC NC D1 SS SS PNC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SASASA C SA SA SA TMS TDI Note: The following pins are reserved for higher densities: 10A for 72Mb and 2A for 144Mb. 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. H 1/6/2010