IS61QDB22M18A IS61QDB21M36A 2Mx18, 1Mx36 JANUARY 2015 36Mb QUAD (Burst 2) Synchronous SRAM DESCRIPTION FEATURES The Mb and are 1Mx36 and 2Mx18 configuration available. synchronous, high-performance CMOS static random access On-chip Delay-Locked Loop (DLL) for wide data memory (SRAM) devices. These SRAMs have separate I/Os, valid window. eliminating the need for high-speed bus turnaround. The Separate independent read and write ports with rising edge of K clock initiates the read/write operation, and concurrent read and write operations. all internal operations are self-timed. Refer to the Synchronous pipeline read with EARLY write for a description of the operation. basic operations of these SRAMs. Double Data Rate (DDR) interface for read and The input address bus operates at double data rate. The write input ports. following are registered internally on the rising edge of the K Fixed 2-bit burst for read and write operations. clock: Clock stop support. Read address Two input clocks (K and K ) for address and control Read enable registering at rising edges only. Write enable Two output clocks (C and C ) for data output control. Byte writes Two echo clocks (CQ and CQ ) that are delivered Data-in for early writes simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used The following are registered on the rising edge of the K with 0.75, 0.9V VREF. clock: HSTL input and output interface. Write address Registered addresses, write and read controls, byte Byte writes writes, data in, and data outputs. Data-in for second burst addresses Full data coherency. Boundary scan using limited set of JTAG 1149.1 Byte writes can change with the corresponding data-in to functions. enable or disable writes on a per-byte basis. An internal write Byte write capability. buffer enables the data-ins to be registered half a cycle Fine ball grid array (FBGA) package: earlier than the write address. The first data-in burst is 13mmx15mm and 15mmx17mm body size clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the 165-ball (11 x 15) array K clock. Programmable impedance output drivers via 5x user-supplied precision resistor. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the C clock (starting 1.5 cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the C clock. The K and K clocks are used to time the data-outs whenever the C and C clocks are tied high. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. B 10/02/2014 IS61QDB22M18B IS61QDB21M36B Package ballout and description x36 FBGA BALL CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 1 1 1 A CQ NC/SA NC/SA W BW K BW R SA NC/SA CQ 2 1 B Q27 Q18 D18 SA BW K BW SA D17 Q17 Q8 3 0 C D27 Q28 D19 V SA SA SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: The following balls are reserved for higher densities: 3A for 72Mb, 10A for 144Mb, and 2A for 288Mb. x18 FBGA BALL CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 1 1 1 A CQ NC/SA SA W BW K NC/SA R SA NC/SA CQ 1 B NC Q9 D9 SA NC K BW SA NC NC Q8 0 C NC NC D10 V SA SA SA V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC D14 V V V V V NC Q4 D4 DDQ DD SS DD DDQ K NC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ L NC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ M NC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS N NC D17 Q16 V SA SA SA V NC NC D1 SS SS P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: 1. The following balls are reserved for higher densities: 10A for 72Mb, 2A for 144Mb, and 7A for 288Mb. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. B 10/02/2014