IS61QDB42M18A IS61QDB41M36A 2Mx18, 1Mx36 36Mb QUAD (Burst 4) SYNCHRONOUS SRAM JANUARY 2014 FEATURES DESCRIPTION The 36Mb IS61QDB41M36A and IS61QDB42M18A are 1Mx36 and 2Mx18 configuration available. synchronous, high-performance CMOS static random access On-chip Delay-Locked Loop (DLL) for wide data memory (SRAM) devices. These SRAMs have separate I/Os, valid window. eliminating the need for high-speed bus turnaround. The Separate independent read and write ports with rising edge of K clock initiates the read/write operation, and concurrent read and write operations. all internal operations are self-timed. Refer to the Timing Synchronous pipeline read with late write operation. Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Double Data Rate (DDR) interface for read and write input ports. Read and write addresses are registered on alternating rising 1.5 cycle read latency. edges of the K clock. Reads and writes are performed in Fixed 4-bit burst for read and write operations. double data rate. The following are registered internally on Clock stop support. the rising edge of the K clock: Two input clocks (K and K ) for address and control Read/write address registering at rising edges only. Read enable Two output clocks (C and C ) for data output control. Write enable Two echo clocks (CQ and CQ ) that are delivered Byte writes for burst addresses 1 and 3 simultaneously with data. Data-in for burst addresses 1 and 3 +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. The following are registered on the rising edge of the K HSTL input and output levels. clock: Byte writes for burst addresses 2 and 4 Registered addresses, write and read controls, byte writes, data in, and data outputs. Data-in for burst addresses 2 and 4 Full data coherency. Byte writes can change with the corresponding data-in to Boundary scan using limited set of JTAG 1149.1 enable or disable writes on a per-byte basis. An internal write functions. buffer enables the data-ins to be registered one cycle after Byte write capability. the write address. The first data-in burst is clocked one cycle Fine ball grid array (FBGA) package: later than the write command signal, and the second burst is 13mmx15mm and 15mmx17mm body size timed to the following rising edge of the K clock. Two full 165-ball (11 x 15) array clock cycles are required to complete a write operation. Programmable impedance output drivers via 5x During the burst read operation, the data-outs from the first user-supplied precision resistor. and third bursts are updated from output registers of the second and third rising edges of the C clock (starting 1.5 cycles later after read command). The data-outs from the second and fourth bursts are updated with the third and fourth rising edges of the C clock. The K and K clocks are used to time the data-outs whenever the C and C clocks are tied high. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A1 1/15/2014 IS61QDB42M18A IS61QDB41M36A Package ballout and description x36 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 1 A CQ NC/SA NC/SA W BW K BW R SA NC/SA CQ 2 1 B Q27 Q18 D18 SA BW K BW SA D17 Q17 Q8 3 0 C D27 Q28 D19 V SA NC SA V D16 Q7 D8 SS SS D D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS E Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ F Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ G D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ K Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ L Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ M D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS N D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: The following balls are reserved for higher densities: 3A for 72Mb, 10A for 144Mb, and 2A for 288Mb. x18 FBGA Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 1 A CQ NC/SA SA W BW K NC/SA R SA NC/SA CQ 1 B NC Q9 D9 SA NC K BW SA NC NC Q8 0 C NC NC D10 V SA NC SA V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ H Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ L NC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ M NC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS N NC D17 Q16 V SA SA SA V NC NC D1 SS SS P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: 1. The following balls are reserved for higher densities: 10A for 72Mb, 2A for 144Mb, and 7A for 288Mb. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A1 1/15/2014