IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM JANUARY 2016 (2.5 Cycle Read Latency) FEATURES DESCRIPTION The 72Mb IS61QDPB42M36A/A1/A2 and 2Mx36 and 4Mx18 configuration available. IS61QDPB44M18A/A1/A2 are synchronous, high- On-chip Delay Locked Loop (DLL) for wide data performance CMOS static random access memory (SRAM) valid window. devices. These SRAMs have separate I/Os, eliminating the Separate independent read and write ports with need for high-speed bus turnaround. The rising edge of K concurrent read and write operations. clock initiates the read/write operation, and all internal Synchronous pipeline read with late write operation. operations are self-timed. Refer to the Timing Reference Double Data Rate (DDR) interface for read and Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write input ports. write addresses are registered on alternating rising edges of 2.5 cycle read latency. the K clock. Reads and writes are performed in double data Fixed 4-bit burst for read and write operations. rate. Clock stop support. The following are registered internally on the rising edge of Two input clocks (K and K ) for address and control the K clock: registering at rising edges only. Read/write address Two echo clocks (CQ and CQ ) that are delivered simultaneously with data. Read enable Data Valid Pin (QVLD). Write enable +1.8V core power supply and 1.5, 1.8V VDDQ, used Byte writes for burst addresses 1 and 3 with 0.75, 0.9V VREF. Data-in for burst addresses 1 and 3 HSTL input and output interface. Registered addresses, write and read controls, byte The following are registered on the rising edge of the K clock: writes, data in, and data outputs. Byte writes for burst addresses 2 and 4 Full data coherency. Data-in for burst addresses 2 and 4 Boundary scan using limited set of JTAG 1149.1 functions. Byte writes can change with the corresponding data-in to Byte write capability. enable or disable writes on a per-byte basis. An internal write Fine ball grid array (FBGA) package buffer enables the data-ins to be registered one cycle after 13mm x 15mm & 15mm x 17mm body size the write address. The first data-in burst is clocked one cycle 165-ball (11 x 15) array later than the write command signal, and the second burst is timed to the following rising edge of the K clock. Two full Programmable impedance output drivers via 5x clock cycles are required to complete a write operation. user-supplied precision resistor. ODT (On Die Termination) feature is supported During the burst read operation, the data-outs from the first optionally on data input, K/K , and BW . x and third bursts are updated from output registers of the third The end of top mark (A/A1/A2) is to define options. and fourth rising edges of the K clock (starting 2.5 cycles IS61QDPB42M36A : Dont care ODT function later after read command). The data-outs from the second and pin connection and fourth bursts are updated with the fourth and fifth rising edges of the K clock where the read command receives at IS61QDPB42M36A1: Option1 the first rising edge of K. Two full clock cycles are required to IS61QDPB42M36A2: Option2 complete a read operation. Refer to more detail description at page 6 for each ODT option. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. E1 12/01/2015 IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 Package ballout and description x36 FBGA Ball ballout (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 CQ NC/SA SA W BW K BW R SA NC/SA CQ 2 1 A Q27 Q18 D18 SA BW K BW SA D17 Q17 Q8 3 0 B D27 Q28 D19 V SA NC SA V D16 Q7 D8 SS SS C D28 D20 Q19 V V V V V Q16 D15 D7 SS SS SS SS SS D Q29 D29 Q20 V V V V V Q15 D6 Q6 DDQ SS SS SS DDQ E Q30 Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ F D30 D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ G Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF H D31 Q31 D23 V V V V V D12 Q4 D4 DDQ DD SS DD DDQ J Q32 D32 Q23 V V V V V Q12 D3 Q3 DDQ DD SS DD DDQ K Q33 Q24 D24 V V V V V D11 Q11 Q2 DDQ SS SS SS DDQ L D33 Q34 D25 V V V V V D10 Q1 D2 SS SS SS SS SS M D34 D26 Q25 V SA SA SA V Q10 D9 D1 SS SS N Q35 D35 Q26 SA SA QVLD SA SA Q9 D0 Q0 P TDO TCK SA SA SA ODT SA SA SA TMS TDI R The following balls are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb. x18 FBGA Ball ballout (Top View) 1 2 3 4 5 6 7 8 9 10 11 1 1 CQ NC/SA SA W BW K NC/SA R SA SA CQ 1 A NC Q9 D9 SA NC K BW SA NC NC Q8 0 B NC NC D10 V SA NC SA V NC Q7 D8 SS SS C NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS D NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ E NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ F NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ G Doff V V V V V V V V V ZQ REF DDQ DDQ DD SS DD DDQ DDQ REF H NC NC D14 V V V V V NC Q4 D4 DDQ DD SS DD DDQ J NC NC Q14 V V V V V NC D3 Q3 DDQ DD SS DD DDQ K NC Q15 D15 V V V V V NC NC Q2 DDQ SS SS SS DDQ L NC NC D16 V V V V V NC Q1 D2 SS SS SS SS SS M NC D17 Q16 V SA SA SA V NC NC D1 SS SS N NC NC Q17 SA SA QVLD SA SA NC D0 Q0 P TDO TCK SA SA SA ODT SA SA SA TMS TDI R Notes: 1. The following balls are reserved for higher densities: 2A for 144Mb, and 7A for 288Mb. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. E1 12/01/2015