IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B IS61LF102418B/IS61VF102436B/IS61VVF102418B 512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM OCTOBER 2015 FEATURES DESCRIPTION Internal self-timed write cycle The 18Mb product family features high-speed, low- Individual Byte Write Control and Global Write power synchronous static RAMs designed to provide Clock controlled, registered address, data and burstable, high-performance memory for control communication and networking applications. The Burst sequence control using MODE input IS61(64)LF/VF/VVF51236(32)B organized as 524,288 Three chip enable option for simple depth words by 36(32)bits. The IS61(64)LF/VF/VVF102418B expansion and address pipelining are organized as 1,048,576 words by 18 bits. Common data inputs and data outputs Fabricated with ISSI s advanced CMOS technology, Auto Power-down during deselect the device integrates a 2-bit burst counter, high-speed Single cycle deselect SRAM core, and high-drive capability outputs into a Snooze MODE for reduced-power standby single monolithic circuit. All synchronous inputs pass JEDEC 100-pin QFP, 165-ball BGA and 119-ball through registers controlled by a positive-edge- BGA packages triggered single clock input. Power supply: LF: V 3.3V ( 5%), V 3.3V/2.5V ( 5%) Write cycles are internally self-timed and are initiated DD DDQ VF: V 2.5V ( 5%), V 2.5V ( 5%) by the rising edge of the clock input. Write cycles can DD DDQ VVF: V 1.8V ( 5%), V 1.8V ( 5%) be one to four bytes wide as controlled by the write DD DDQ JTAG Boundary Scan for BGA packages control inputs. Commercial, Industrial and Automotive temperature support Separate byte enables allow individual bytes to be Lead-free available written. The byte write operation is performed by using For leaded options, please contact ISSI the byte write enable (/BWE) input combined with one or more individual byte write signals (/BWx). In addition, Global Write (/GW) is available for writing all FAST ACCESS TIME bytes at one time, regardless of the byte write controls. Symbol Parameter -6.5 -7.5 Units Bursts can be initiated with either /ADSP (Address Clock Access Status Processor) or /ADSC (Address Status Cache t 6.5 7.5 ns KQ Time Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the /ADV t Cycle time 7.5 8.5 ns KC (burst address advance) input pin. Frequency 133 117 MHz The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. C 09/12/2015 IS61LF51236(32)B/IS61VF51236(32)B/IS61VVF51236(32)B IS61LF102418B/IS61VF102436B/IS61VVF102418B BLOCK DIAGRAM E Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. C 09/12/2015