IS61vPS25672A IS61lPS25672A IS61vPS51236A IS61lPS51236A IS61vPS102418A IS61lPS102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPElINED, JUl Y 2017 SINglE CYClE DESElECT STATIC RAM FEATURES DESCRIPTION The ISSI IS61LPS/VPS51236A, IS61LPS/VPS102418A, Inter nal self-timed wr ite cycle and IS61LPS/VPS25672A are high-speed, low-power Individual Byte Wr ite Control and Global Wr ite synchronous static RAMs designed to provide burstable, high-perfor mance memory for communication and network- Clock controlled, registered address, data and ing applications. The IS61LPS/VPS51236A is organized control as 524,288 words by 36 bits, the IS61LPS/VPS102418A is Burst sequence control using MODE input organized as 1,048,576 words by 18 bits, and the IS61LPS/ VPS25672A is organized as 262,144 words by 72 bits. Three chip enable option for simple depth ex- Fabr icated with ISSI s advanced CMOS technology, the pansion and address pipelining device integrates a 2-bit burst counter, high-speed SRAM core, and high-dr ive capability outputs into a single mono- Common data inputs and data outputs lithic circuit. All synchronous inputs pass through registers Auto Power-down dur ing deselect controlled by a positive-edge-tr iggered single clock input. Single cycle deselect Wr ite cycles are inter nally self-timed and are initiated by the r ising edge of the clock input. Wr ite cycles can be one Snooze MODE for reduced-power standby to four bytes wide as controlled by the write control inputs. JTAG Boundar y Scan for PBGA package Separate byte enables allow individual bytes to be written. The byte wr ite operation is perfor med by using the byte wr ite Power Supply enable (BWE) input combined with one or more individual LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% byte wr ite signals (BWx). In addition, Global Wr ite (GW) is available for writing all bytes at one time, regardless of VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% the byte write controls. JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball Bursts can be initiated with either ADSP (Address Status PBGA, and 209-ball (x72) packages Processor) or ADSC (Address Status Cache Controller) Lead-free available input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Inter leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 250 200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1-800-379-4774 1 Rev. Q 07/19/2017IS61VPS25672A, IS61LPS25672A IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A BLOCK DIAGRAM MODE A0 Q0 A0 CLK CLK BINARY COUNTER A1 Q1 ADV CE A1 256Kx72 ADSC 512Kx36 CLR ADSP 1024Kx18 MEMORY ARRAY 19/20 17/18 19/20 D Q A ADDRESS REGISTER CE CLK 36, 36, or 18 or 18 or 72 or 72 GW D Q DQ(a-h) BWE BYTE WRITE BW(a-h) REGISTERS x18: a,b x36: a-d CLK x72: a-h 36, CE 2/4/8 or 18 INPUT OUTPUT or 72 CE2 D Q REGISTERS REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY POWER REGISTER ZZ DOWN CLK OE 2 Integrated Silicon Solution, Inc. 1-800-379-4774 Rev. Q 07/19/2017