IS61WV12816BLL IS64WV12816BLL ISSI 128K x 16 HIGH-SPEED CMOS STATIC RAM FEBRUARY 2006 FEATURES DESCRIPTION The ISSI IS61WV12816BLL and IS64WV12816BLL are High-speed access time: high-speed, 2,097,152-bit static RAM organized as 131,072 12 ns: 3.3V + 10% words by 16 bits. They are fabricated using ISSI s high- 15 ns: 2.5V-3.6V performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields Operating Current: 25mA (typ.) access times as fast as 12 ns with low power consumption. Stand by Current: 400A(typ.) When CE is HIGH (deselected), the device assumes a TTL and CMOS compatible interface levels standby mode at which the power dissipation can be Fully static operation: no clock or refresh reduced down with CMOS input levels. required Easy memory expansion is provided by using Chip Enable Three state outputs and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the Data control for upper and lower bytes memory. A data byte allows Upper Byte (UB) and Lower Industrial and Automotive temperatures avail- Byte (LB) access. able The IS61WV12816BLL and IS64WV12816BLL are packaged Lead-free available in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM 128Kx16 A0-A16 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CE OE CONTROL WE CIRCUIT UB LB Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. C 02/03/06IS61WV12816BLL IS64WV12816BLL ISSI TRUTH TABLE I/O PIN Mode WEWEWE CECECE OEOEOE LBLBLB UBUBUB I/O0-I/O7 I/O8-I/O15 VDD Current WEWE CECE OEOE LBLB UBUB Not Selected X H X X X High-Z High-Z ISB1, ISB2 Output Disabled H L H X X High-Z High-Z ICC X L X H H High-Z High-Z Read H L L L H DOUT High-Z ICC H L L H L High-Z DOUT H LLLL DOUT DOUT Write L L X L H DIN High-Z ICC L L X H L High-Z DIN LL X L L DIN DIN PIN CONFIGURATION 44-Pin TSOP (Type II) (T) PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs A4 1 44 A5 A3 2 43 A6 CE Chip Enable Input A2 3 42 A7 OE Output Enable Input A1 4 41 OE A0 5 40 UB WE Write Enable Input CE 6 39 LB LB Lower-byte Control (I/O0-I/O7) I/O0 7 38 I/O15 I/O1 8 37 I/O14 UB Upper-byte Control (I/O8-I/O15) I/O2 9 36 I/O13 I/O3 10 35 I/O12 NC No Connection VDD 11 34 GND VDD Power GND 12 33 VDD I/O4 13 32 I/O11 GND Ground I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. C 02/03/06