IS61WV12816DALL/DALS IS61WV12816DBLL/DBLS IS64WV12816DBLL/DBLS 128K x 16 HIGH SPEED ASYNCHRONOUS JULY 2011 CMOS STATIC RAM FEATURES DESCRIPTION The ISSI IS61WV12816DAxx/DBxx and IS64WV12816DBxx HIGH SPEED: (IS61/64WV12816DALL/DBLL) are high-speed, 2,097,152-bit static RAMs organized as High-speed access time: 8, 10, 12, 20 ns 131,072 words by 16 bits. It is fabricated using ISSI s high- Low Active Power: 135 mW (typical) performance CMOS technology. This highly reliable pro- cess coupled with innovative circuit design techniques, Low Standby Power: 12 W (typical) yields high-performance and low power consumption de- CMOS standby vices. LOW POWER: (IS61/64WV12816DALS/DBLS) High-speed access time: 25, 35 ns When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be Low Active Power: 55 mW (typical) reduced down with CMOS input levels. Low Standby Power: 12 W (typical) CMOS standby Easy memory expansion is provided by using Chip Enable Single power supply and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the VDD 1.65V to 2.2V (IS61WV12816DAxx) memory. A data byte allows Upper Byte (UB) and Lower VDD 2.4V to 3.6V (IS61/64WV12816DBxx) Byte (LB) access. Fully static operation: no clock or refresh required The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are packaged in the JEDEC standard 44-pin TSOP Type II and Three state outputs 48-pin Mini BGA (6mm x 8mm). Data control for upper and lower bytes Industrial and Automotive temperature support Lead-free available FUNCTIONAL BLOCK DIAGRAM 128K x 16 A0-A16 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CE OE CONTROL WE CIRCUIT UB LB Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. D 06/21/2011IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS TRUTH TABLE I/O PIN Mode WEWEWE CECECE OEOEOE LBLBLB UBUBUB I/O0-I/O7 I/O8-I/O15 VDD Current WEWE CECE OEOE LBLB UBUB Not Selected X H X X X High-Z High-Z ISB1, ISB2 Output Disabled H L H X X High-Z High-Z ICC X L X H H High-Z High-Z Read H L L L H DOUT High-Z ICC H L L H L High-Z DOUT H LLLL DOUT DOUT Write L L X L H DIN High-Z ICC L L X H L High-Z DIN LL X L L DIN DIN PIN CONFIGURATION PIN DESCRIPTIONS 44-Pin TSOP (Type II) (T) A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs A4 1 44 A5 A3 2 43 A6 CE Chip Enable Input A2 3 42 A7 OE Output Enable Input A1 4 41 OE A0 5 40 UB WE Write Enable Input CE 6 39 LB LB Lower-byte Control (I/O0-I/O7) I/O0 7 38 I/O15 I/O1 8 37 I/O14 UB Upper-byte Control (I/O8-I/O15) I/O2 9 36 I/O13 I/O3 10 35 I/O12 NC No Connection VDD 11 34 GND VDD Power GND 12 33 VDD I/O4 13 32 I/O11 GND Ground I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 20 25 A14 A10 A13 21 24 A11 A12 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. D 06/21/2011