IS61WV12816EDBLL IS64WV12816EDBLL 128K x 16 HIGH SPEED ASYNCHRONOUS MAY 2020 CMOS STATIC RAM WITH ECC DESCRIPTION FEATURES The ISSI IS61/64WV12816EDBLL is a high-speed, High-speed access time: 8, 10 ns 2,097,152-bit static RAMs organized as 131,072 words Low Active Power: 85 mW (typical) by 16 bits. It is fabricated using ISSI s high-performance Low Standby Power: 7 mW (typical) CMOS technology. This highly reliable process coupled CMOS standby with innovative circuit design techniques, yields high- performance and low power consumption devices. Single power supply Vdd 2.4V to 3.6V (10 ns) When CE is HIGH (deselected), the device assumes a Vdd 3.3V 10% (8 ns) standby mode at which the power dissipation can be re- Fully static operation: no clock or refresh duced down with CMOS input levels. required Easy memory expansion is provided by using Chip Enable Three state outputs and Output Enable inputs, CE and OE. The active LOW Data control for upper and lower bytes Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Industrial and Automotive temperature support Byte (LB) access. Lead-free available Error Detection and Error Correction The IS61/64WV12816EDBLL is packaged in the JEDEC standard 44-pin TSOP-II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM Memory Memory A0-A16 ECC ECC Lower IO Upper IO Array- Array- Decoder 128K 128K Array- Array- x4 x4 128Kx8 128Kx8 8 4 8 4 8 8 12 IO0-7 ECC I/O Data 8 8 12 Column I/O Circuit IO8-15 ECC /CE /OE Control /WE Circuit /UB /LB Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A1 05/27/2020IS61/64WV12816EDBLL TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X High-Z High-Z Isb 1, Isb 2 Output Disabled H L H X X High-Z High-Z Icc X L X H H High-Z High-Z Read H L L L H d out High-Z Icc H L L H L High-Z d out H L L L L d out d out Write L L X L H d In High-Z Icc L L X H L High-Z d In L L X L L d In d In PIN CONFIGURATION 44-Pin TSOP (Type II) (T) PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs A4 1 44 A5 A3 2 43 A6 CE Chip Enable Input A2 3 42 A7 OE Output Enable Input A1 4 41 OE A0 5 40 UB WE Write Enable Input CE 6 39 LB LB Lower-byte Control (I/O0-I/O7) I/O0 7 38 I/O15 UB Upper-byte Control (I/O8-I/O15) I/O1 8 37 I/O14 I/O2 9 36 I/O13 NC No Connection I/O3 10 35 I/O12 Vdd Power VDD 11 34 GND GND Ground GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A1 05/27/2020