IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEBRUARY 2017 DESCRIPTION FEATURES The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx HIGH SPEED: (IS61/64WV25616ALL/BLL) are high-speed, 4,194,304-bit static RAMs organized as High-speed access time: 8, 10, 20 ns 262,144 words by 16 bits. It is fabricated using ISSI s high- Low Active Power : 85 mW (typical) perfor mance CMOS technology. This highly reliable process Low Standby Power : 7 mW (typical) coupled with innovative circuit design techniques, yields CMOS standby high-performance and low power consumption devices. LOW POWER: (IS61/64WV25616ALS/BLS) When CE is HIGH (deselected), the device assumes a High-speed access time: 25, 35, 45 ns standby mode at which the power dissipation can be re- Low Active Power : 35 mW (typical) duced down with CMOS input levels. Low Standby Power : 0.6 mW (typical) CMOS standby Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Single power supply Write Enable (WE) controls both writing and reading of the Vdd 1.65V to 2.2V (IS61WV25616Axx) memory. A data byte allows Upper Byte (UB) and Lower Vdd 2.4V to 3.6V (IS61/64WV25616Bxx) Byte (LB) access. Fully static operation: no clock or refresh required The IS61WV25616Axx/Bxx and IS64WV25616Bxx are Three state outputs packaged in the JEDEC standard 44-pin 400mil SOJ, Data control for upper and lower bytes 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). Industr ial and Automotive temperature suppor t Lead-free available FUNCTIONAL BLOCK DIAGRAM 256K x 16 A0-A17 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CE OE CONTROL WE CIRCUIT UB LB Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. H1 02/10/2017IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X High-Z High-Z Isb 1, Isb 2 Output Disabled H L H X X High-Z High-Z Icc X L X H H High-Z High-Z Read H L L L H d out High-Z Icc H L L H L High-Z d out H L L L L d out d out Write L L X L H d In High-Z Icc L L X H L High-Z d In L L X L L d In d In PIN CONFIGURATIONS PIN DESCRIPTIONS A0-A17 Address Inputs 44-Pin TSOP (Type II) and SOJ I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input A0 1 44 A17 WE Write Enable Input A1 2 43 A16 A2 3 42 A15 LB Lower-byte Control (I/O0-I/O7) A3 4 41 OE UB Upper-byte Control (I/O8-I/O15) 40 UB A4 5 CE 6 39 LB NC No Connection I/O0 7 38 I/O15 Vdd Power I/O1 8 37 I/O14 I/O2 9 36 I/O13 GND Ground I/O3 10 35 I/O12 VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A5 18 27 A14 A6 19 26 A13 A7 20 25 A12 A8 21 24 A11 A9 22 23 A10 *soJ package under evaluation. 2 Integrated Silicon Solution, Inc. www.issi.com Rev. H1 02/10/2017