IS61/64WV25616FALL IS61/64WV25616FBLL JANUARY 2021 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM KEY FEATURES DESCRIPTION ISSI High-speed access time: 8, 10ns, 12ns The IS61/64WV25616FALL/FBLL are high-speed, low power, 4M bit static RAMs organized as 256K words by 16 Low Active Current: 35mA (Max., 10ns, I-temp) bits. It is fabricated using ISSI s high-performance CMOS Low Standby Current: 10 mA (Max., I-temp) technology. Single power supply This highly reliable process coupled with innovative circuit 1.65V-2.2V VDD (IS61/64WV25616FALL) design techniques, yields high-performance and low power 2.4V-3.6V VDD (IS61/64WV25616FBLL) devices. Three state outputs When CS is HIGH (deselected), the device assumes a Data Control for upper and lower bytes standby mode at which the power dissipation can be reduced down with CMOS input levels. Industrial and Automotive temperature support Easy memory expansion is provided by using Chip Enable Lead-free available and Output Enable inputs. The active LOW Write Enable (WE ) controls both writing and reading of the memory. A data byte allows Upper Byte (UB ) and Lower Byte (LB ) FUNCTIONAL BLOCK DIAGRAM access. The IS61/64WV25616FALL/FBLL are packaged in the 256K x 16 JEDEC standard 48-ball mini BGA (6mm x 8mm), 44-pin MEMORY DECODER A0 A17 400mil SOJ, and 44-pin TSOP (TYPE II) ARRAY VDD GND I/O I/O0 I/O7 DATA COLUMN I/O CIRCUIT I/O8 I/O15 CS OE CONTROL WE CIRCUIT UB LB Copyright 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A2 01/11/2021 IS61/64WV25616FALL IS61/64WV25616FBLL PIN CONFIGURATIONS 48-Ball mini BGA(6mm x 8mm), 48-Ball mini BGA (6mm x 8mm) , Switched IO (Package Code : B) (Package Code : B2) 1 2 3 4 5 6 1 2 3 4 5 6 A A LB OE A0 A1 A2 NC LB OE A0 A1 A2 NC B B I/O8 UB A3 A4 CS I/O0 I/O0 UB A3 A4 CS I/O8 I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O1 I/O2 A5 A6 I/O10 I/O9 C D D VSS I/O11 A17 A7 I/O3 VDD VSS I/O3 A17 A7 I/O11 VDD E VDD I/O12 NC A16 I/O4 VSS E VDD I/O4 NC A16 I/O12 VSS F F I/O14 I/O13 A14 A15 I/O5 I/O6 I/O6 I/O5 A14 A15 I/O13 I/O14 G G I/O15 NC A12 I/O7 A13 WE I/O7 NC A12 I/O15 A13 WE H NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC 44-Pin TSOP-II and SOJ, (Package Code : T and K) PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS Chip Enable Input 1 A17 A0 44 43 A16 A1 2 OE Output Enable Input A2 3 42 A15 WE Write Enable Input 4 41 OE A3 5 40 UB A4 LB Lower-byte Control 39 LB CS 6 (I/O0-I/O7) 7 38 I/O15 I/O0 UB Upper-byte Control 8 37 I/O14 I/O1 I/O13 I/O2 9 36 (I/O8-I/O15) I/O12 I/O3 10 35 NC No Connection VDD VSS 11 34 VSS 12 33 VDD VDD Power I/O4 13 32 I/O11 VSS Ground 14 31 I/O10 I/O5 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A5 18 27 A14 A13 19 26 A6 A7 A12 20 25 21 24 A11 A8 23 A9 22 A10 Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A2 01/11/2021