IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS 256K x 32 HIGH-SPEED ASYNCHRONOUS PRELIMINARY INFORMATION CMOS STATIC RAM WITH 3.3V SUPPLY APRIL 2008 FEATURES DESCRIPTION The ISSI IS61WV25632Axx/Bxx and IS64WV25632Bxx High-speed access times: are high-speed, 8M-bit static RAMs organized as 256K 8, 10, 20 ns words by 32 bits. It is fabricated using ISSI s high-per- High-performance, low-power CMOS process formance CMOS technology. This highly reliable process Multiple center power and ground pins for coupled with innovative circuit design techniques, yields greater noise immunity high-performance and low power consumption devices. Easy memory expansion with CE and OE op- tions When CE is HIGH (deselected), the device assumes CE power-down a standby mode at which the power dissipation can be reduced down with CMOS input levels. Fully static operation: no clock or refresh required Easy memory expansion is provided by using Chip Enable TTL compatible inputs and outputs and Output Enable inputs, CE and OE. The active LOW Single power supply Write Enable (WE) controls both writing and reading of Vdd 1.65V to 2.2V (IS61WV25632Axx) the memory. speed = 20ns for Vdd 1.65V to 2.2V Vdd 2.4V to 3.6V (IS61/64WV25632Bxx) The device is packaged in the JEDEC standard 90-ball BGA (8mm x 13mm). speed = 10ns for Vdd 2.4V to 3.6V speed = 8ns for Vdd 3.3V + 5% Packages available: 90-ball miniBGA (8mm x 13mm) Industrial and Automotive Temperature Support Lead-free available FUNCTIONAL BLOCK DIAGRAM 256K x 32 A0-A17 DECODER MEMORY ARRAY VDD VSS DQa-d I/O COLUMN I/O DATA CIRCUIT CE OE CONTROL WE CIRCUIT BWa-d CE2 Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. 00B 04/23/08IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS PIN CONFIGURATION PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch) 1 2 3 4 5 6 7 8 9 A DQ1 DQ0 VSS VDD DQ31 DQ30 B DQ2 VDD VSS VDD VSS DQ29 C VSS DQ3 DQ4 DQ27 DQ28 VDD D VSS DQ6 DQ5 DQ26 DQ25 VDD E VDD DQ7 NC NC DQ24 VSS F VSS BWa A3 A4 BWd VDD G A0 A1 A2 A10 A5 A6 H A15 A14 A13 A8 A7 A11 J CE2 A17 A16 A9 A12 CE K BWb NC NC WE OE BWc L VDD DQ8 VSS DQ23 VDD VSS M VSS DQ9 DQ10 DQ22 DQ21 VDD N VSS DQ12 DQ11 DQ19 DQ20 VDD P DQ13 VDD VSS VSS VDD DQ18 R DQ14 DQ15 VSS DQ16 VDD DQ17 PIN DESCRIPTIONS A0-A17 Address Inputs DQx Data I/O CE, CE2 Chip Enable Input OE Output Enable Input WE Write Enable Input BWx (x=a-d) Byte Write Control Vdd Power Vss Ground NC No Connection 2 Integrated Silicon Solution, Inc. www.issi.com Rev. 00B 04/23/08