IS61WV2568EDBLL IS64WV2568EDBLL 256K x 8 HIGH SPEED ASYNCHRONOUS DECEMBER 2011 CMOS STATIC RAM WITH ECC DESCRIPTION FEATURES The I S S I IS61/64WV2568EDBLL is a high-speed, High-speed access time: 8, 10 ns 2,097,152-bit static RAMs organized as 262,144 words by Low Active Power: 85 mW (typical) 8 bits. It is fabricated using ISSI s high-performance CMOS Low Standby Power: 7 mW (typical) technology. This highly reliable process coupled with inno- CMOS standby vative circuit design techniques, yields high-performance and low power consumption devices. Single power supply Vdd 2.4V to 3.6V (10 ns) When CE is HIGH (deselected), the device assumes a Vdd 3.3V 10% (8 ns) standby mode at which the power dissipation can be re- Fully static operation: no clock or refresh duced down with CMOS input levels. required Easy memory expansion is provided by using Chip Enable Three state outputs and Output Enable inputs, CE and OE. The active LOW Industrial and Automotive temperature support Write Enable (WE) controls both writing and reading of the memory. Lead-free available Error Detection and Error Correction The IS61/64WV2568EDBLL is packaged in the JEDEC standard 44-pin TSOP-II, 36-pin SOJ and 36-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM ECC Array Memory Array A0-A17 Decoder (256Kx4) (256Kx8) 8 4 8 8 12 I/O Data IO0-7 ECC Column I/O Circuit /CE Control /OE Circuit /WE Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A 11/08/2011IS61/64WV2568EDBLL PIN CONFIGURATION 36 mini BGA 44-Pin TSOP (Type II) 1 2 3 4 5 6 NC 1 44 NC NC 2 43 NC A0 3 42 NC A1 4 41 A17 A2 5 40 A16 A3 6 39 A15 A A0 A1 NC A3 A6 A8 A4 7 38 A14 B I/O4 A2 WE A4 A7 I/O0 CE 8 37 OE I/O0 9 36 I/O7 C I/O5 NC A5 I/O1 I/O1 10 35 I/O6 D GND VDD VDD 11 34 GND GND 12 33 VDD E VDD GND I/O2 13 32 I/O5 F I/O6 NC A17 I/O2 I/O3 14 31 I/O4 WE 15 30 A13 I/O7 OE A16 A15 I/O3 G CE A5 16 29 A12 A9 A10 A12 A13 A14 17 28 H A11 A6 A11 A7 18 27 A10 26 A8 19 NC A9 20 25 NC 24 NC 21 NC NC 22 23 NC 36-Pin SOJ PIN DESCRIPTIONS A0 1 36 NC A0-A17 Address Inputs A1 2 35 A17 CE Chip Enable Input A2 3 34 A16 OE Output Enable Input A3 4 33 A15 WE Write Enable Input A4 5 32 A14 CE 6 31 OE I/O0-I/O7 Bidirectional Ports I/O0 7 30 I/O7 Vdd Power I/O1 8 29 I/O6 GND Ground VDD 9 28 GND NC No Connection 27 GND 10 VDD I/O2 11 26 I/O5 I/O3 12 25 I/O4 WE 13 24 A13 A5 14 23 A12 A6 15 22 A11 A7 16 21 A10 A8 17 20 NC A9 18 19 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A 11/08/2011