IS61WV6416EEBLL IS64WV6416EEBLL 64K x 16 HIGH SPEED ASYNCHRONOUS MARCH 2020 CMOS STATIC RAM WITH ECC DESCRIPTION FEATURES The ISSI IS61/64WV6416EEBLL is a high-speed, High-speed access time: 8, 10 ns 1,048,576-bit static RAMs organized as 65,536 words by 16 Low Active Power: 85 mW (typical) bits. It is fabricated using ISSI s high-performance CMOS Low Standby Power: 7 mW (typical) technology. This highly reliable process coupled with in- CMOS standby novative circuit design techniques, yields high-performance and low power consumption devices. Single power supply Fully static operation: no clock or refresh When CE is HIGH (deselected), the device assumes a required standby mode at which the power dissipation can be re- Three state outputs duced down with CMOS input levels. Data control for upper and lower bytes Easy memory expansion is provided by using Chip Enable Industrial and Automotive temperature support and Output Enable inputs, CE and OE. The active LOW Lead-free available Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Error Detection and Error Correction Byte (LB) access. The IS61/64WV6416EEBLL is packaged in the JEDEC standard 44-pin TSOP-II, 48-pin Mini BGA (6mm x 8mm), and 44-pin SOJ. FUNCTIONAL BLOCK DIAGRAM Memory Memory A0-A15 ECC ECC Lower IO Upper IO Array- Array- Decoder 64K 64K Array- Array- x4 x4 64Kx8 64Kx8 8 4 8 4 8 8 12 IO0-7 ECC I/O Data 8 8 12 Column I/O Circuit IO8-15 ECC /CE /OE Control /WE Circuit /UB /LB Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A2 03/11/2020IS61/64WV6416EEBLL TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X High-Z High-Z Isb 1, Isb 2 Output Disabled H L H X X High-Z High-Z Icc X L X H H High-Z High-Z Read H L L L H Dout High-Z Icc H L L H L High-Z Dout H L L L L Dout Dout Write L L X L H DIn High-Z Icc L L X H L High-Z DIn L L X L L DIn DIn PIN CONFIGURATIONS 44-Pin TSOP-II PIN DESCRIPTIONS A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input 44 A0 A15 1 43 A1 A14 2 OE Output Enable Input 42 A2 A13 3 WE Write Enable Input 41 OE A12 4 LB Lower-byte Control (I/O0-I/O7) 40 UB A11 5 39 LB CE 6 UB Upper-byte Control (I/O8-I/O15) 38 I/O15 I/O0 7 NC No Connection 37 I/O14 I/O1 8 VDD Power 36 I/O13 I/O2 9 35 I/O12 I/O3 10 GND Ground 34 GND VDD 11 33 VDD GND 12 32 13 I/O11 I/O4 31 I/O10 I/O5 14 30 I/O9 I/O6 15 29 I/O8 I/O7 16 28 NC WE 17 27 A3 A10 18 26 A4 A9 19 25 A8 20 A5 24 A6 A7 21 23 NC NC 22 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A2 03/11/2020