IS62C25616BL, IS65C25616BL 256Kx 16 HIGH-SPEED CMOS ST ATICRAM MARCH2013 FEATURES DESCRIPTION The ISSI IS62C25616BL and IS65C25616BL are high- High-speed access time: 45 ns speed, 4,194,304-bit static RAMs organized as 262,144 Low Active Pow er50: mW (typical) words by 16 bits. They are fabricated using ISSI s high- Low Standby Pow er10: Wm (typical) performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields CMOS standby access times as fast as 12 ns with low power consumption. TTL compatible interface levels Single 5V 10% power supply When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced Fully static operation: no clock or refresh down with CMOS input levels. required Package: 44-pinTSOP (Type II) Easy memory expansion is provided by using Chip Enable Commercial, Industrial and Automotive temper- and Output Enable inputs, CE and OE. The active LOW ature ranges available Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Lead-free available Byte (LB) access. The IS62C25616BL and IS65C25616BL are packaged in the JEDEC standard 44-pinTSOP (Type II). FUNCTIONAL BLOCK DIAGRAM 256K x 16 A0-A17 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CE OE CONTROL WE CIRCUIT UB LB Copyright 2013 Integrated Silicon Solution, Inc.All rights reserv ed.ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services descrCustomersibed herein. are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effProductsectiveness are. not authorized for use in such applications unless Integrated Silicon Solution, Inc.receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. B 03/15/2013IS62C25616BL, IS65C25616BL PIN CONFIGURATIONS* 44-Pin TSOP(T ypeII) 44 A5 A4 1 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 A17 *Please contact ISSI at SRAM issi.com for availability of 48-pin BGA and 44-pin SOJ packages. PINDESCRIPTIONS A0-A17 Address Inputs LB Lower-byte Control (I/O0-I/O7) I/O0-I/O15 Data Inputs/Outputs UB Upper-byte Control (I/O8-I/O15) CE Chip Enable Input NC No Connection OE Output Enable Input Vdd Power WE Write Enable Input GND Ground 2 1-800-379-4774 Integrated Silicon Solution, Inc. www.issi.com Rev. B 03/15/2013