IS62WV12816ALL IS62WV12816BLL 128K x 16 LOW VOLTAGE, NOVEMBER 2013 ULTRA LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION High-speed access time: 45ns, 55ns, 70ns The ISSI IS62WV12816ALL/ IS62WV12816BLL are high- speed, 2M bit static RAMs organized as 128K words by CMOS low power operation 16 bits. It is fabricated using ISSI s high-performance 36 mW (typical) operating CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high- 9 W (typical) CMOS standby performance and low power consumption devices. TTL compatible interface levels When CS1 is HIGH (deselected) or when CS2 is LOW Single power supply (deselected) or when CS1 is LOW, CS2 is HIGH and both 1.65V--2.2V Vdd (62WV12816ALL) LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with 2.5V--3.6V Vdd (62WV12816BLL) CMOS input levels. Fully static operation: no clock or refresh Easy memory expansion is provided by using Chip Enable required and Output Enable inputs. The active LOW Write Enable Three state outputs (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) Data control for upper and lower bytes access. Industrial temperature available The IS62WV12816ALL and IS62WV12816BLL are 2CS Option Available packaged in the JEDEC standard 48-pin mini BGA (6mm Lead-free available x 8mm) and 44-Pin TSOP (TYPE II). FUNCTIONAL BLOCK DIAGRAM 128K x 16 A0-A16 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 CONTROL OE CIRCUIT WE UB LB Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly af fect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. J 11/19/2013IS62WV12816ALL, IS62WV12816BLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) (Package Code B) 1 2 3 4 5 6 1 2 3 4 5 6 A LB OE A0 A1 A2 N/C A LB OE A0 A1 A2 CS2 I/O UB A3 A4 CSI I/O I/O UB A3 A4 CS1 I/O B 8 0 B 8 0 I/O I/O A5 A6 I/O I/O I/O I/O A5 A6 I/O I/O 9 10 1 2 9 10 1 2 C C GND I/O NC A7 I/O VDD GND I/O NC A7 I/O VDD D 11 3 D 11 3 VDD I/O NC A16 I/O GND VDD I/O NC A16 I/O GND E 12 4 E 12 4 I/O I/O A14 A15 I/O I/O I/O I/O A14 A15 I/O I/O F 14 13 5 6 F 14 13 5 6 A12 A12 I/O15 NC A13 WE I/O I/O15 NC A13 WE I/O G 7 G 7 NC A8 A9 A10 A11 NC NC A8 A9 A10 A11 NC H H 44-Pin mini TSOP (Type II) PIN DESCRIPTIONS (Package Code T) A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input A4 1 44 A5 A3 2 43 A6 OE Output Enable Input A2 3 42 A7 A1 4 41 OE WE Write Enable Input A0 5 40 UB CS1 6 39 LB LB Lower-byte Control (I/O0-I/O7) I/O0 7 38 I/O15 UB Upper-byte Control (I/O8-I/O15) I/O1 8 37 I/O14 I/O2 9 36 I/O13 NC No Connection I/O3 10 35 I/O12 VDD 11 34 GND Vdd Power GND 12 33 VDD I/O4 13 32 I/O11 GND Ground I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 A15 19 26 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. J 11/19/2013