IS62WV12816EALL IS62/65WV12816EBLL MAY 2017 128Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES DESCRIPTION The ISSI IS62/65WV12816EALL/EBLL are high-speed, 2M High-speed access time: 45ns, 55ns bit static RAMs organized as 128K words by 16 bits. It is fabricated using ISSI s high-performance CMOS technology. CMOS low power operation This highly reliable process coupled with innovative circuit Operating Current: 18 mA (max) at 85C design techniques, yields high-performance and low power CMOS Standby Current: 5.4uA (typ) at 25C consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW TTL compatible interface levels (deselected) or when CS1 is LOW, CS2 is HIGH and both Single power supply LB and UB are HIGH, the device assumes a standby 1.65V-2.2V VDD (IS62WV12816EALL) mode at which the power dissipation can be reduced down 2.2V-3.6V VDD (IS62/65WV12816EBLL) with CMOS input levels. Three state outputs Easy memory expansion is provided by using Chip Enable Industrial and Automotive temperature support and Output Enable inputs. The active LOW Write Enable Lead-free available (WE ) controls both writing and reading of the memory. A data byte allows Upper Byte (UB ) and Lower Byte (LB ) access. The IS62/65WV12816EALL/EBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II) BLOCK DIAGRAM 128K x 16 MEMORY DECODER A0 A16 ARRAY VDD GND I/O0 I/O7 I/O Lower Byte DATA COLUMN I/O I/O8 I/O15 CIRCUIT Upper Byte CS2 CS1 CONTROL OE CIRCUIT WE UB LB Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. C2 05/24/2017 IS62WV12816EALL IS62/65WV12816EBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 48-Pin mini BGA (6mm x 8mm) (Package Code B) 2 CS Option (Package Code B2) 1 2 3 4 5 6 1 2 3 4 5 6 A A LB OE3 A0 A1 A2 NC LB OE3 A0 A1 A2 CS2 B B I/O8 UB A3 A4 CS1 I/O0 I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 I/O9 I/O10 A5 A6 I/O1 I/O2 C D D GND I/O11 NC A7 I/O3 VDD GND I/O11 NC A7 I/O3 VDD D VDD I/O12 NC A16 I/O4 GND D VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 G G I/O15 NC A12 A13 WE I/O7 I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS 44-Pin mini TSOP (Type II) (Package Code T) A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs 1 A4 44 A5 43 A3 2 A6 CS1 , Chip Enable Input 3 42 A7 A2 CS2 41 OE A1 4 5 40 UB OE Output Enable Input A0 39 LB CS 6 WE Write Enable Input 38 7 I/O15 I/O0 37 I/O14 LB Lower-byte Control 8 I/O1 I/O2 9 I/O13 36 (I/O0-I/O7) 10 35 I/O12 I/O3 UB Upper-byte Control VDD GND 11 34 (I/O8-I/O15) GND 12 33 VDD 32 I/O11 I/O4 13 NC No Connection I/O5 I/O10 14 31 30 I/O9 VDD Power I/O6 15 29 I/O8 I/O7 16 GND Ground 28 NC WE 17 A8 A16 18 27 A15 26 A9 19 A10 A14 25 20 A13 21 24 A11 A12 23 NC 22 Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. C2 05/24/2017