IS62WV2568ALL IS62WV2568BLL JANUARY 2010 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION The ISSI IS62WV2568ALL / IS62WV2568BLL are high- High-speed access time: 45ns, 55ns, 70ns speed, 2M bit static RAMs organized as 256K words CMOS low power operation by 8 bits. It is fabr icated using ISSI s high-performance CMOS technology. This highly reliable process coupled 36 mW (typical) operating with innovative circuit design techniques, yields high- 9 W (typical) CMOS standby performance and low power consumption devices. TTL compatible interface levels When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) , the device assumes a standby mode at Single power supply which the power dissipation can be reduced down with CMOS input levels. 1.65V--2.2V Vcc (62WV2568ALL) Easy memory expansion is provided by using Chip Enable 2.5V--3.6V Vcc (62WV2568BLL) and Output Enable inputs. The active LOW Wr ite Enable Fully static operation: no clock or refresh (WE) controls both writing and reading of the memory. required The IS62WV2568ALL and IS62WV2568BLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP Three state outputs (TYPE I), and 36-pin mini BGA. Industr ial temperature available Lead-free available FUNCTIONAL BLOCK DIAGRAM 256K x 8 A0-A17 DECODER MEMORY ARRAY VCC GND I/O COLUMN I/O DATA I/O0-I/O7 CIRCUIT CS2 CS1 CONTROL CIRCUIT OE WE Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. H 1/6/10IS62WV2568ALL, IS62WV2568BLL PIN DESCRIPTIONS A0-A17 Address Inputs CS1 Chip Enable 1 Input CS2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output NC No Connection Vcc Power GND Ground PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm) 32-pin TSOP (TYPE I), sTSOP (TYPE I) 1 2 3 4 5 6 A11 1 32 OE A9 2 31 A10 A8 3 30 CS1 A A0 A1 CS2 A3 A6 A8 A13 4 29 I/O7 WE 5 28 I/O6 B I/O4 A2 WE A4 A7 I/O0 CS2 6 27 I/O5 C I/O5 NC A5 I/O1 A15 7 26 I/O4 VCC 8 25 I/O3 GND Vcc D 24 GND A17 9 Vcc GND E A16 10 23 I/O2 A14 11 22 I/O1 F I/O6 NC A17 I/O2 A12 12 21 I/O0 I/O7 OE CS1 A16 A15 I/O3 G A7 13 20 A0 A6 14 19 A1 A9 A10 A12 A13 A14 A11 H A5 15 18 A2 A4 16 17 A3 2 Integrated Silicon Solution, Inc. www.issi.com Rev. H 1/6/10