IS62WV51216EFALL/BLL IS65WV51216EFALL/BLL FEBURARY 2020 512Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM with ECC KEY FEATURES DESCRIPTION The ISSI IS62/65WV51216EFALL/BLL are high-speed, low High-speed access time: 45ns, 55ns power, 8M bit static RAMs organized as 512K words by 16 CMOS low power operation bits. It is fabricated using ISSI s high-performance CMOS Operating Current: 35mA (max.) technology and implemented ECC function to improve CMOS standby Current: 5.5uA (typ.) reliability. TTL compatible interface levels This highly reliable process coupled with innovative circuit design techniques including ECC (SEC-DEC: Single Error Single power supply Correcting-Double Error Detecting), yields high- 1.65V-2.2V VDD (IS62/65WV51216EFALL) performance and low power consumption devices. When 2.2V-3.6V VDD (IS62/65WV51216EFBLL) CS1 is HIGH (deselected) or when CS2 is LOW (deselected), or when CS1 is LOW, CS2 is HIGH and Optional ERR1/ERR2 pin: both LB and UB are HIGH, the device assumes a ERR1: indicates 1-bit error detection and standby mode at which the power dissipation can be correction. reduced down with CMOS input levels. ERR2: indicates 2-bit error detection Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable Three state outputs (WE ) controls both writing and reading of the memory. A Commercial, Industrial and Automotive data byte allows Upper Byte (UB ) and Lower Byte (LB ) temperature support access. Lead-free available The IS62/65WV51216EFALL/BLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm), and 44-pin FUNCTIONAL BLOCK DIAGRAM TSOP (TYPE II) Memory Memory Lower IO ECC Upper IO ECC DECODER Array Array Array Array A0 A18 512Kx8 512Kx4 512Kx8 512Kx4 VDD VSS 8 5 8 5 ERR1 ERR2 13 8 I/O0 I/O7 I/O ECC DATA COLUMN I/O Column I/O 13 8 ECC CIRCUIT I/O8 I/O15 CS1 CS2 CONTROL OE CIRCUIT WE UB LB Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A4 02/11/2020 IS62WV51216EFALL/BLL IS65WV51216EFALL/BLL PIN CONFIGURATIONS 48-Pin mini BGA(6mm x 8mm), 2CS, No ERR 48-Pin mini BGA (6mm x 8mm),2CS, ERR1, ERR2 1 2 3 4 5 6 1 2 3 4 5 6 A A LB OE A0 A1 A2 CS2 LB OE A0 A1 A2 CS2 B B I/O8 UB A3 A4 CS1 I/O0 I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 D D VSS I/O11 A17 A7 I/O3 VDD VSS I/O11 A17 A7 I/O3 VDD E VDD I/O12 ERR1 A16 I/O4 VSS E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 ERR2 A12 A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1 , CS2 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) ERR1 Single ERR Correction Signal ERR2 Double ERR Detection Signal NC No Connection VDD Power VSS Ground Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A4 02/11/2020