IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, JANUARY 2008 ULTRA LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION The ISSI IS62WV6416ALL/ IS62WV6416BLL are high- High-speed access time: 45ns, 55ns speed, 1M bit static RAMs organized as 64K words by 16 CMOS low power operation: bits. It is fabricated using ISSI s high-performance CMOS technology. This highly reliable process coupled with 30 mW (typical) operating innovative circuit design techniques, yields high- 15 W (typical) CMOS standby performance and low power consumption devices. TTL compatible interface levels When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both Single power supply LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with 1.7V--2.2V VDD (62WV6416ALL) CMOS input levels. 2.5V--3.6V VDD (62WV6416BLL) Easy memory expansion is provided by using Chip Enable Fully static operation: no clock or refresh and Output Enable inputs. The active LOW Write Enable required (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) Three state outputs access. Data control for upper and lower bytes The IS62WV6416ALL and IS62WV6416BLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and Industrial temperature available 44-Pin TSOP (TYPE II). 2CS Option Available Lead-free available FUNCTIONAL BLOCK DIAGRAM 64K x 16 A0-A15 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 OE CONTROL CIRCUIT WE UB LB Copyright 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. C 01/14/08IS62WV6416ALL, IS62WV6416BLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) (Package Code B) 1 2 3 4 5 6 1 2 3 4 5 6 A LB OE A0 A1 A2 NC A LB OE A0 A1 A2 CS2 I/O UB A3 A4 I/O UB A3 A4 B 8 CSI I/O0 B 8 CS1 I/O0 I/O9 I/O A5 A6 I/O I/O I/O9 I/O A5 A6 I/O I/O C 10 1 2 C 10 1 2 GND I/O NC A7 I/O VDD GND I/O NC A7 I/O VDD D 11 3 D 11 3 VDD I/O NC NC I/O GND VDD I/O NC NC I/O GND 12 4 12 4 E E I/O A14 I/O I/O A14 I/O 14 I/O A15 5 I/O 14 I/O A15 5 I/O F 13 6 F 13 6 I/O NC A12 A13 WE I/O I/O NC A12 A13 WE I/O 15 7 15 7 G G NC A10 NC A10 A8 A9 A11 NC A8 A9 A11 NC H H 44-Pin mini TSOP (Type II) (Package Code T) PIN DESCRIPTIONS A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs A4 1 44 A5 CS1, CS2 Chip Enable Input A3 2 43 A6 A2 3 42 A7 OE Output Enable Input A1 4 41 OE A0 5 40 UB WE Write Enable Input CS1 6 39 LB I/O0 7 38 I/O15 LB Lower-byte Control (I/O0-I/O7) I/O1 8 37 I/O14 I/O2 9 36 I/O13 UB Upper-byte Control (I/O8-I/O15) I/O3 10 35 I/O12 VDD 11 34 GND NC No Connection GND 12 33 VDD I/O4 13 32 I/O11 VDD Power I/O5 14 31 I/O10 I/O6 15 30 I/O9 GND Ground I/O7 16 29 I/O8 WE 17 28 NC A15 18 27 A8 A14 19 26 A9 A13 20 25 A10 A12 21 24 A11 NC 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. C 01/14/08