IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL 64K x 16 LOW VOLTAGE, DECEMBER 2012 ULTRA LOW POWER CMOS STATIC RAM FEATURES DESCRIPTION The ISSI IS62/65WV6416DALL and IS62/65WV6416DBLL High-speed access time: 35ns, 45ns, 55ns are high-speed, 1M bit static RAMs organized as 64K words CMOS low power operation: by 16 bits. It is fabr icated using ISSI s high-perfor mance CMOS technology. This highly reliable process coupled 15 mW (typical) operating with innovative circuit design techniques, yields high- 1.5 W (typical) CMOS standby perfor mance and low power consumption devices. TTL compatible interface levels When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both Single power supply LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with 1.65V--2.2V Vdd (62WV6416d ALL) CMOS input levels. 2.3V--3.6V Vdd (65WV6416BLL)d Easy memor y expansion is provided by using Chip Enable Fully static operation: no clock or refresh and Output Enable inputs. The active LOW Wr ite Enable required (WE) controls both wr iting and reading of the memor y. A data byte allows Upper Byte (UB) and Lower Byte (LB) Three state outputs access. Data control for upper and lower bytes The IS62/65WV6416DALL and IS62/65WV6416DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm Industr ial and automotive temperature suppor t x 8mm) and 44-Pin TSOP (TYPE II). 2CS Option Available Lead-free available FUNCTIONAL BLOCK DIAGRAM 64K x 16 A0-A15 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 OE CONTROL CIRCUIT WE UB LB Integrated Silicon Solution, Inc. www.issi.com 1 Rev. B 12/18/12IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) (Package Code B) 1 2 3 4 5 6 1 2 3 4 5 6 A LB OE A0 A1 A2 NC A LB OE A0 A1 A2 CS2 I/O UB A3 A4 CSI I/O I/O UB A3 A4 CS1 I/O B 8 0 B 8 0 I/O I/O A5 A6 I/O I/O I/O I/O A5 A6 I/O I/O 9 10 1 2 9 10 1 2 C C GND I/O NC A7 I/O VDD GND I/O NC A7 I/O VDD D 11 3 D 11 3 VDD I/O NC NC I/O GND VDD I/O NC NC I/O GND E 12 4 E 12 4 I/O A14 I/O I/O A14 I/O F 14 I/O13 A15 5 I/O6 F 14 I/O13 A15 5 I/O6 I/O NC A12 A13 WE I/O I/O NC A12 A13 WE I/O G 15 7 G 15 7 NC A8 A10 NC A8 A10 A9 A11 NC A9 A11 NC H H 44-Pin mini TSOP (Type II) (Package Code T) PIN DESCRIPTIONS A0-A15 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input A4 1 44 A5 OE Output Enable Input A3 2 43 A6 A2 3 42 A7 WE Wr ite Enable Input A1 4 41 OE A0 5 40 UB LB Lower-byte Control (I/O0-I/O7) CS1 6 39 LB I/O0 7 38 I/O15 UB Upper-byte Control (I/O8-I/O15) I/O1 8 37 I/O14 NC No Connection I/O2 9 36 I/O13 35 I/O3 10 I/O12 Vdd Power VDD 11 34 GND GND 12 33 VDD GND Ground I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A15 18 27 A8 A14 19 26 A9 A13 20 25 A10 A12 21 24 A11 NC 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. B 12/18/12