IS62/65WVS0648FALL IS62/65WVS0648FBLL JULY 2021 64Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION SPI-Compatible Bus Interface: The ISSI IS62/65WVS0648FALL/BLL are 512K bit Serial - 16/20 MHz Clock rate static RAMs organized as 64K bytes by 8 bits. It is fabricated using ISSI s high-performance CMOS - SPI/SDI/SQI mode technology. Low-Power CMOS Technology: The device is accessed via a simple Serial Peripheral - Read Current: 8 mA(max) at 3.6V, 20 MHz, 85C Interface (SPI) compatible serial bus. The bus signals - CMOS Standby Current: 4 uA (typ). required are a clock input (SCK) plus separate data in 64K x 8-bit Organization: (SI) and data out (SO) lines. Access the device is - 32-byte page controlled through a Chip Select (CS ) input. Byte, Page and Sequential mode for Reads and Additionally, SDI (Serial Dual Interface) and SQI (Serial Writes Quad Interface) is supported if your application needs Temperature Ranges Supported: faster data rates. - Industrial (I): -40C to +85C This device also supports unlimited reads and writes to - Automotive (A3): -40C to +125C the memory array. RoHS Compliant - 8-pin SOIC package The IS62/65WVS5128FALL/FBLL are available in the standard 8-pin SOIC package. Copyright 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A5 07/06/2021 IS62/65WVS0648FALL IS62/65WVS0648FBLL BLOCK DIAGRAM Control Logic Status I/O Buffers and Register Data Latches CS SCK SI (SIO0) Y- Decoder SO (SIO1) DNU (SIO2) HOLD X (SIO3) Memory Array Decoder 64Kb x 8 Address Latch& Counter Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A5 07/06/2021 Serial Peripheral Interface