IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A DECEMBER 2013 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINgLE CYCLE DESELECT STATIC RAM FEATURES DESCRIPTION The ISSI IS61(64)LPS12832A, IS61(64)LPS/VP- Inter nal self-timed wr ite cycle S12836A and IS61(64)LPS/VPS25618A are high-speed, Individual Byte Wr ite Control and Global Wr ite low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication Clock controlled, registered address, data and and networ king applications. The IS61(64)LPS12832A is control organized as 131,072 words by 32 bits. The IS61(64)LPS/ Burst sequence control using MODE input VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/VPS25618A is organized as 262,144 Three chip enable option for simple depth ex- words by 18 bits. Fabr icated with ISSI s advanced CMOS pansion and address pipelining technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-dr ive capability outputs Common data inputs and data outputs into a single monolithic circuit. All synchronous inputs pass Auto Power-down dur ing deselect through registers controlled by a positive-edge-triggered single clock input. Single cycle deselect Wr ite cycles are inter nally self-timed and are initiated by Snooze MODE for reduced-power standby the r ising edge of the clock input. Wr ite cycles can be one Power Supply to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% The byte wr ite operation is perfor med by using the byte VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global JEDEC 100-Pin QFP, 119-ball and 165-ball Wr ite (GW) is available for writing all bytes at one time, BGA packages regardless of the byte write controls. Automotive temperature available Bursts can be initiated with either ADSP (Address Status Lead Free available Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence or- der, Linear burst is achieved when this pin is tied LOW. Inter leave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol Parameter 250 200 Units tkq Clock Access Time 2.6 3.1 ns tkc Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil- ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. H1 12/06/2013IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A BLOCK DIAGRAM MODE A0 Q0 CLK CLK A0 BINARY COUNTER A1 Q1 ADV CE A1 128Kx32 ADSC 128Kx36 CLR ADSP 256Kx18 MEMORY ARRAY 17/18 15/16 17/18 A D Q ADDRESS REGISTER CE CLK 32, 36, 32, 36, or 18 or 18 GW D Q DQ(a-d) BWE BYTE WRITE BW(a-d) REGISTERS x18: a,b x32/x36: a-d CLK 32, 36, CE 2/4/8 or 18 INPUT OUTPUT CE2 D Q REGISTERS REGISTERS DQa - DQd CE2 ENABLE OE REGISTER CLK CLK CE CLK D Q ENABLE DELAY POWER REGISTER ZZ DOWN CLK OE 2 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013