IS61WV12816DALL/DALS IS61WV12816DBLL/DBLS IS64WV12816DBLL/DBLS 128K x 16 HIGH SPEED ASYNCHRONOUS JANUARY 2013 CMOS STATIC RAM DESCRIPTION FEATURES The ISSI IS61WV12816DAxx/DBxx and IS64WV12816D- HIGH SPEED: (IS61/64WV12816DALL/DBLL) Bxx are high-speed, 2,097,152-bit static RAMs organized High-speed access time: 8, 10, 12, 20 ns as 131,072 words by 16 bits. It is fabr icated using ISSI s Low Active Power : 135 mW (typical) high-perfor mance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, Low Standby Power : 12 W (typical) yields high-performance and low power consumption CMOS standby devices. LOW POWER: (IS61/64WV12816DALS/DBLS) High-speed access time: 25, 35 ns When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be re- Low Active Power : 55 mW (typical) duced down with CMOS input levels. Low Standby Power : 12 W (typical) CMOS standby Easy memor y expansion is provided by using Chip Enable Single power supply and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the Vdd 1.65V to 2.2V (IS61WV12816DAxx) memory. A data byte allows Upper Byte (UB) and Lower Vdd 2.4V to 3.6V (IS61/64WV12816DBxx) Byte (LB) access. Fully static operation: no clock or refresh The IS61WV12816DAxx/DBxx and IS64WV12816DBxx required are packaged in the JEDEC standard 44-pin TSOP Type Three state outputs II and 48-pin Mini BGA (6mm x 8mm). Data control for upper and lower bytes Industr ial and Automotive temperature suppor t Lead-free available FUNCTIONAL BLOCK DIAGRAM 128K x 16 A0-A16 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 I/O Lower Byte COLUMN I/O DATA CIRCUIT I/O8-I/O15 Upper Byte CE OE CONTROL WE CIRCUIT UB LB Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with - out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. E 01/10/2013IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X High-Z High-Z Isb 1, Isb 2 Output Disabled H L H X X High-Z High-Z Icc X L X H H High-Z High-Z Read H L L L H d out High-Z Icc H L L H L High-Z d out H L L L L d out d out Write L L X L H d In High-Z Icc L L X H L High-Z d In L L X L L d In d In PIN CONFIGURATION 44-Pin TSOP (Type II) (T) PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs 44 A4 1 A5 CE Chip Enable Input A3 2 43 A6 OE Output Enable Input A2 3 42 A7 WE Write Enable Input A1 4 41 OE A0 5 40 UB LB Lower-byte Control (I/O0-I/O7) CE 6 39 LB UB Upper-byte Control (I/O8-I/O15) I/O0 7 38 I/O15 I/O1 8 37 I/O14 NC No Connection I/O2 9 36 I/O13 Vdd Power 35 I/O12 I/O3 10 GND Ground VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A16 18 27 A8 26 A15 19 A9 A14 20 25 A10 A13 21 24 A11 A12 22 23 NC 2 Integrated Silicon Solution, Inc. www.issi.com Rev. E 01/10/2013