IS66WV1M16EBLL-70BLI ISSI

IS66WV1M16EALL IS66/67WV1M16EBLL SEPTEMBER 2018 16Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM DESCRIPTION Features The ISSI IS66WV1M16EALL and IS66/67WV1M16EBLL are High-Speed access time : high-speed,16M bit static RAMs organized as 1M words by - 70ns ( IS66WV1M16EALL ) 16 bits. It is fabricated using ISSIs high performance CMOS - 60ns (IS66/67WV1M16EBLL ) technology. CMOS Lower Power Operation This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power Single Power Supply consumption devices. VDD =1.7V~1.95V( IS66WV1M16EALL ) When CS1 is HIGH (deselected) or when CS2 is LOW (deselected), the device assumes a standby mode at which VDD =2.5V~3.6V (IS66/67WV1M16EBLL ) the power dissipation can be reduced down with CMOS input levels. Three State Outputs Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE ) Data Control for Upper and Lower bytes controls both writing and reading of the memory. A data byte Lead-free Available allows Upper Byte (UB ) and Lower Byte (LB ) access. The IS66WV1M16 EALL and IS66/67WV1M16EBLL are packaged in the JEDEC standard 48-ball mini BGA (6mm x 8mm). The device is also available for die sales. FUNCTIONAL BLOCK DIAGRAM Address A0~A19 Decode Logic 1M X 16 VDD DRAM Memory Array GND I/O0-I/O7 COLUMN Lower Byte I/O DATA I/O CIRCUIT I/O8-I/O15 Upper Byte CS2 CS1 Control OE WE Logic UB LB Copyright 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assu mes no liability arising out of the application oruse of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 Rev. B3 09/17/2018 www.issi.com - SRAM issi.comIS66WV1M16EALL IS66/67WV1M16EBLL PIN CONFIGURATIONS 48-Ball miniBGA (6mm x 8mm) Ball Assignment 1 2 3 4 5 6 LB OE A0 A1 A2 CS2 A I/Q8 UB A3 A4 CS1 I/Q0 B I/Q9 I/Q10 A5 A6 I/Q1 IQ2 C GND IQ11 A17 A7 I/Q3 VDD D VDD IQ12 NC A16 I/Q4 GND E I/Q14 I/Q13 A14 A15 I/Q5 I/Q6 F I/Q15 A19 A12 A13 WE I/Q7 G A18 A8 A9 A10 A11 NC H Notes : 1. TSOP package option is under evaluation. PIN DESCRIPTIONS Symbol Type Description A0~A19 Input Address Inputs I/Q0~I/Q15 Input / Data Inputs/Outputs Output CS1 , CS2 Input Chip Enable OE Input Output Enable WE Input Write Enable UB Input Upper Byte select LB Input Lower Byte select VDD Power Supply Power GND Power Supply Ground 2 Rev. B3 09/17/2018 www.issi.com - SRAM issi.com