IS66WVC2M16EALL/CLL IS67WVC2M16EALL/CLL 32Mb Async/Page/Burst CellularRAM 1.5 Overview The IS66WVC2M16EALL/CLL is an integrated memory device containing 32Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several power saving modes : Reduced Array Refresh mode where data is retained in a portion of the array and Temperature Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a standard asynchronous mode and high performance burst mode. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Features Single device supports asynchronous , page, Low Power Consumption and burst operation Asynchronous Operation < 30 mA Mixed Mode supports asynchronous write and Intrapage Read < 20mA synchronous read operation Burst operation < 45 mA ( 133Mhz) Dual voltage rails for optional performance Standby < 150 uA(max.) ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V Deep power-down (DPD) < 3uA (Typ) CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V Low Power Feature Asynchronous mode read access : 70ns Reduced Array Refresh Interpage Read access : 70ns Temperature Controlled Refresh Intrapage Read access : 25ns Deep power-down (DPD) mode Burst mode for Read and Write operation Operation Frequency up to 133Mhz 4, 8, 16,32 or Continuous Operating temperature Range Industrial -40C~85C Package: 54-ball VFBGA Copyright 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. 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A1 Oct. 2016 www.issi.com SRAM issi.com IS66WVC2M16EALL/CLL IS67WVC2M16EALL/CLL General Description CellularRAM (Trademark of MicronTechnology Inc.) products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 32Mb DRAM core device is organized as 2 Meg x 16 bits. This device is a variation of the industry-standard Flash control interface that dramatically increase READ/WRITE bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products have incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the refresh rate to match the device temperature the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are adjusted through the RCR. This CellularRAM device is compliant with the industry-standard CellularRAM 1.5 feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three drive strengths, a variety of wrap options, and a device ID register (DIDR). A0~A20 Address Decode Logic Input 2048K X 16 /Output Refresh Configuration Register DRAM Mux (RCR) Memory Array And Buffers Device ID Register (DIDR) Bus Configuration Register (BCR) CE WE OE CLK Control ADV Logic CRE LB DQ0~DQ15 UB WAIT Functional Block Diagram 2 Rev. A1 Oct. 2016 www.issi.com SRAM issi.com