IS66WVE2M16TCLL-70BLI-TR ISSI

IS66/67WVE4M16EALL/BLL/CLL IS66/67WVE4M16TALL/BLL/CLL 64Mb Async/Page PSRAM AUGUST 2018 Overview The IS66/67WVE4M16EALL/BLL/CLL and IS66/67WVE4M16TALL/BLL/CLL integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Features Asynchronous and page mode interface Low Power Feature Dual voltage rails for optional performance Temperature Controlled Refresh ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V Partial Array Refresh BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V Deep power-down (DPD) mode CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V Operating temperature Range Page mode read access Industrial: -40C~85C Interpage Read access : 60ns, 70ns Automotive A1: -40C~85C Intrapage Read access : 25ns Automotive A2: -40C~105C Low Power Consumption Asynchronous Operation < 30 mA Packages: Intrapage Read < 23mA 48-ball TFBGA Standby < 200 uA (max.) at -40C~85C Deep power-down (DPD) ALL/CLL: < 3A (Typ) BLL: < 10A (Typ) Notes: 1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM Marketing at sram issi.com for additional information. Copyright 2018 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 Rev. D2 August 2018 www.issi.com - SRAM issi.comIS66/67WVE4M16EALL/BLL/CLL IS66/67WVE4M16TALL/BLL/CLL General Description PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration registers (CR) defines how the PSRAM device performs on- chip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. Special attention has been focused on current consumption during self-refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable (ZZ ) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR. A0~A21 Address Decode Logic Input 4096K X 16 /Output DRAM Mux Memory Array And Configuration Register Buffers (CR) CE WE Control OE Logic LB UB ZZ DQ0~DQ15 Functional Block Diagram 2 Rev. D2 August 2018 www.issi.com - SRAM issi.com