PDM41256SA15SOI IXYS

PDM41256 256K Static RAM 32K x 8-Bit 1 Features Description The PDM41256 is a high-performance CMOS static n High-speed access times RAM organized as 32,768 x 8 bits. Writing to this 2 Coml: 7, 8, 10, 12 and 15ns device is accomplished when the write enable (WE) Indl: 8, 10, 12 and 15ns and the chip enable (CE) inputs are both LOW. (use 15ns for slower designs) Reading is accomplished when WE remains HIGH n Low power operation (typical) and CE and OE are both LOW. - PDM41256SA 3 Active: 475 mW The PDM41256 operates from a single +5V power Standby: 100 mW supply and all the inputs and outputs are fully TTL- - PDM41256LA compatible. The PDM41256 comes in two versions: Active: 425mW 4 the standard power version PDM41256SA and the Standby: 25 mW low power version PDM41256LA. Both versions are functionally the same and differ only in their power n Single +5V ( 10%) power supply consumption. n TTL-compatible inputs and outputs 5 The PDM41256 is available in a 28-pin plastic TSOP n Packages (I) and a 28-pin 300-mil plastic SOJ. Plastic SOJ (300 mil) - SO Plastic TSOP (I) - T 6 Functional Block Diagram 7 A 0 Decoder Memory 8 Addresses Matrix A 14 9 I/O 0 Input Column I/O Data Control 10 I/O 7 11 CE WE 12 OE Rev. 4.4 - 4/29/98 1 PDM41256 SOJ Pin Congurations Pin Description TSOP (I) 1 Vcc A14 28 Name Description A12 2 WE 27 OE 21 A10 22 CE A14-A0 Address Inputs A11 23 20 A7 3 26 A13 A9 19 I/O7 24 A8 A6 4 25 I/O7-I/O0 Data Inputs/Outputs A8 18 I/O6 25 I/O5 A13 26 17 A5 5 24 A9 OE Output Enable Input I/O4 WE 27 16 A4 6 23 A11 Vcc 15 I/O3 28 WE Write Enable Input A14 14 Vss OE 1 A3 7 22 I/O2 A12 2 13 8 21 A10 CE Chip Enable Input A2 I/O1 A7 3 12 A6 11 I/O0 4 A1 9 20 CE V Power (+5V) CC A5 10 A0 5 10 19 I/O7 A0 A1 A4 6 9 V Ground SS A2 18 A3 7 8 11 I/O6 I/O0 12 17 I/O1 I/O5 13 16 I/O2 I/O4 14 15 I/O3 Vss Truth Table OE WE CE I/O MODE X X H Hi-Z Standby LH L D Read OUT XL L D Write IN H H L Hi-Z Output Disable NOTE: 1. H = V , L = V , X = DONT CARE IH IL (1) Absolute Maximum Ratings Symbol Rating Coml. Ind. Unit V Terminal Voltage with Respect to Vss 0.5 to +7.0 0.5 to +7.0 V TERM T Temperature Under Bias 55 to +125 65 to +135 C BIAS T Storage Temperature 55 to +125 65 to +150 C STG P Power Dissipation 1.0 1.0 W T I DC Output Current 50 50 mA OUT (2) T Maximum Junction Temperature 125 145 C j NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: T = T + P * q where T is the ambient tempera- j a ja a ture, P is average operating power and q the thermal resistance of the package. For ja this product, use the following q values: ja o SOJ: 78 C/W o TSOP: 112 C/W 2 Rev. 4.4 - 4/29/98