ispClock 5300S Family In-System Programmable, Zero-Delay Universal Fan-Out Buffer, Single-Ended October 2007 Preliminary Data Sheet DS1010 Up to +/- 5ns skew range Features Coarse and ne adjustment modes Four Operating Congurations Up to Three Clock Frequency Domains Zero delay buffer Zero delay and non-zero delay buffer Flexible Clock Reference and External Dual non-zero delay buffer Feedback Inputs Non-zero delay buffer with output divider Programmable single-ended or differential input reference standards 8MHz to 267MHz Input/Output Operation - LVTTL, LVCMOS, SSTL, HSTL, LVDS, Low Output to Output Skew (<100ps) LVPECL, Differential HSTL, Differential SSTL Low Jitter Peak-to-Peak (< 70 ps) Clock A/B selection multiplexer Up to 20 Programmable Fan-out Buffers Programmable Feedback Standards Programmable single-ended output standards - LVTTL, LVCMOS, SSTL, HSTL and individual enable controls Programmable termination - LVTTL, LVCMOS, HSTL, eHSTL, SSTL Programmable output impedance All Inputs and Outputs are Hot Socket Compliant - 40 to 70 in 5 increments Programmable slew rate Full JTAG Boundary Scan Test In-System Up to 10 banks with individual V and GND CCO Programming Support - 1.5V, 1.8V, 2.5V, 3.3V Exceptional Power Supply Noise Immunity Fully Integrated High-Performance PLL Commercial (0 to 70C) and Industrial Programmable lock detect (-40 to 85C) Temperature Ranges Three Power of 2 output dividers (5-bit) 48-pin and 64-pin TQFP Packages Programmable on-chip loop lter Compatible with spread spectrum clocks Applications Internal/external feedback Circuit board common clock distribution PLL-based frequency generation Precision Programmable Phase Adjustment High fan-out clock buffer (Skew) Per Output Zero-delay clock buffer 8 settings minimum step size 156ps - Locked to VCO frequency ispClock5300S Family Functional Diagram LOCK PLL BYPASS REFA / SKEW OUTPUT + REFP CONTROL DRIVERS OUTPUT REFB / OUTPUT 1 DIVIDERS REFN 1 V0 PHASE LOOP 0 0 5-Bit FREQ. VCO FILTER DETECT 1 V1 5-bit V2 REFSEL OUTPUT 5-bit ROUTING MATRIX FBK OUTPUT N 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 DS1010 01.4 Lattice Semiconductor ispClock5300S Family Data Sheet General Description The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5312S, the rst member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs. Each pair of outputs may be independently congured to support separate I/O standards (LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen- dent programmable control of termination, slew-rate, and timing skew. All conguration information is stored on- 2 chip in non-volatile E CMOS memory. The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32). The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output. The ispClock5300S device can be congured to operate in four modes: zero delay buffer mode, dual non-zero delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay buffer mode. The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the ispClock5300S device family. Table 1. ispClock5300S Family Number of Programmable Number of Programmable Device Clock Inputs Single-Ended Outputs ispClock5320S 1 Differential, 2 Single-Ended 20 ispClock5316S 1 Differential, 2 Single-Ended 16 ispClock5312S 1 Differential, 2 Single-Ended 12 ispClock5308S 1 Differential, 2 Single-Ended 8 ispClock5304S 1 Differential, 2 Single-Ended 4 Figure 1. ispClock5304S Functional Block Diagram LOCK RESET PLL BYPASS OEX OEY VTT REFA LOCK OUTPUT ENABLE VTT REFB DETECT CONTROLS OUTPUT ROUTING SKEW OUTPUT CONTROL MATRIX DRIVERS REFA REFP + BANK 0A OUTPUT REFB REFN DIVIDERS BANK 0B 1 V0 PHASE LOOP 5-bit 0 0 BANK 1A VCO DETECT FILTER 1 BANK 1B V1 5-bit SKEW OUTPUT CONTROL DRIVERS REFSEL V2 5-bit FBK VTT FBK JTAG INTERFACE TDI TMS TCK TDO 2