ispClock 5400D Family
In-System Programmable, Ultra-Low Jitter
Zero Delay and Fan-Out Buffer, Differential
December 2011 Preliminary Data Sheet DS1025
Up to 10 Programmable Fan-out Buffers
Features
Programmable differential output standards and
CleanClock PLL
individual enable controls
- LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
Ultra Low Period Jitter 2.5ps
Up to 10 banks with individual VCCO and GND
Ultra Low Phase Jitter 6.5ps
- 1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
All I/Os are Hot Socket Compliant
Programmable lock detect
Operating Modes
Four output dividers
Fan-out buffer with programmable output skew
Programmable on-chip loop filter
control
Compatible with Spread Spectrum clocks
Zero delay buffer with dual programmable skew
Internal/external feedback
controls
Flexible Clock Reference and External
2
Dynamic Reconfiguration through I C
Feedback Inputs
Programmable differential input reference/feed-
Full JTAG Boundary Scan Test In-System
back standards Programming Support
- LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS
Exceptional Power Supply Noise Immunity
Programmable termination
Commercial (0 to 70C) and Industrial (-40
Clock A/B selection multiplexer
to 85C) Temperature Ranges
FlexiClock I/O 48-Pin and 64-pin QFNS Packages
40 MHz to 400 MHz Input/Output Operation Applications
Low-cost clock source for SERDES
Dual Programmable Skew Per Output
ATCA, MicroTCA, AMC, PCI Express
Programmable phase adjustment
Differential Clock Distribution
- 16 settings; minimum step size 156 ps
Generic Source Synchronous Clock
- Up to +/- 9.4 ns skew range
Management
- Coarse and fine adjustment modes
Zero-delay clock buffer
Programmable time delay adjustment
- 16 settings; 18 ps
2
Dynamic Skew Control Through I C
Low Output-to-Output Skew (<100ps)
ispClock5400D Family Functional Diagram
PLL_BYPASS FlexiClock Output Block
2
I C
Phase Time Differential
Interface
Skew Skew Output
Output
Control* Control T Drivers
V-Dividers
REFSEL +
CleanClock PLL
2
REFA
0
+
4
Phase 0
1
Loop
REFB Freq.
VCO 1
8
+
Filter
Detect
16
+
Output
Routing
Matrix
JTAG
+
+
FBK
Phase Skew
Control
*Available only in PLL mode.
2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 1 DS1025_01.3Lattice Semiconductor ispClock5400D Family Data Sheet
General Description
The ispClock5400D family integrates a CleanClock PLL and a FlexiClock Output block. The CleanClock PLL pro-
vides an ultra-low-jitter clock source to a set of four V-dividers. The FlexiClock output block receives the clock out-
put from these V-dividers through an output switch matrix and distributes them to the output pin using a
programmable logic interface. There are two members in the ispClock5400D family, the ispClock5410D (10-output
FlexiCLock block) and the ispClock5406D (6-output FlexiClock block). Each of the outputs may be independently
configured to support separate I/O standards (LVDS, LVPECL, SSTL, HSTL, MLVDS, HCSL) and output frequency.
In addition, the skew of each of the outputs can be independently controlled. All configuration information is stored
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on-chip in non-volatile E CMOS memory.
The ispClock5400D devices provide extremely low propagation delay (zero-delay) from input to output using the
CleanClock PLL. The PLL VCO output clock frequency is divided down by a set of four V- dividers. The output fre-
quencies from these V-dividers, f 2, f 4, f 8 and f 16 are connected to the output routing
VCO VCO VCO VCO
matrix. The output routing matrix enables any output pin to derive its clock from any of the V-dividers outputs. Addi-
tionally, the reference input clock can be connected directly to any output through the output routing matrix.
The FlexiClock block supports dual skew mechanisms: Phase Skew Control and Time Skew Control. These skew
control mechanisms enable fixed output clock skew control during power-up and variable skew during operation.
The ispClock5400D device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
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The I C interface can be used to dynamically control the ispClock5400D configuration: Output clock frequency,
Phase Skew, Time skew, Fan-out buffer mode, Output enable.
The core functions of both members of the ispClock5400D family are identical. Table 1 summarizes the
ispClock5400D device family.
Table 1. ispClock5400D Family
Number of Programmable Number of Programmable
Device Differential Clock Inputs Differential Outputs
ispClock5410D 2 10
ispClock5406D 2 6
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