ispClock 5500 Family In-System Programmable Clock Generator with Universal Fan-Out Buffer February 2005 Data Sheet Up to Five Clock Frequency Domains Features Flexible Clock Reference Inputs 10MHz to 320MHz Input/Output Operation Programmable input standards Low Output to Output Skew (<50ps) - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL Low Jitter Peak-to-Peak(<70ps) Clock A/B selection multiplexer Up to 20 Programmable Fan-out Buffers Programmable precision termination Programmable output standards and individual enable controls Four User-programmable Proles Stored in 2 - LVTTL, LVCMOS, HSTL, SSTL, LVDS, E CMOS Memory LVPECL Supports both test and multiple operating Programmable precision output impedance congurations - 40 to 70 in 5 increments Full JTAG Boundary Scan Test In-System Programmable slew rate Programming Support Up to 10 banks with individual V and GND CCO Exceptional Power Supply Noise Immunity - 1.5V, 1.8V, 2.5V, 3.3V Commercial (0 to 70C) and Industrial Fully Integrated High-Performance PLL (-40 to 85C) Temperature Ranges Programmable lock detect 100-pin and 48-pin TQFP Packages Multiply and divide ratio controlled by - Input divider (5 bits) Applications - Internal feedback divider (5 bits) Circuit board common clock generation and - Five output dividers (5 bits) distribution Programmable On-chip Loop Filter PLL-based frequency generation High fan-out clock buffer Precision Programmable Phase Adjustment (Skew) Per Output 16 settings minimum step size 195ps - Locked to VCO frequency Up to +/- 12ns skew range Coarse and ne adjustment modes Product Family Block Diagram LOCK DETECT OUTPUT DIVIDERS SKEW OUTPUT CONTROL DRIVERS V0 BYPASS MUX V1 M * PHASE/ V2 FREQUENCY FILTER VCO DETECTOR V3 N OUTPUT V4 ROUTING PLL CORE MATRIX JTAG INTERFACE Multiple Profile Management Logic & 2 E CMOS 021 3 MEMORY INTERNAL FEEDBACK PATH * Input Available only on ispClock 5520 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 clk5500 06.1 REFERENCE INPUTS CLOCK OUTPUTS Lattice Semiconductor ispClock5500 Family Data Sheet General Description and Overview The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5510 provides up to 10 sin- gle-ended or ve differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential clock outputs. Each pair of outputs may be independently congured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro- grammable control of termination, slew-rate, and timing skew. All conguration information is stored on-chip in non- 2 volatile E CMOS memory. The ispClock5500s PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of ve post-PLL V-divid- ers provides additional exibility by supporting the generation of ve separate output frequencies. Loop feedback may be taken from the output of any of the ve V-dividers. The core functions of all members of the ispClock5500 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ispClock5510 and ispClock5520. Table 1. ispClock5500 Family Members Device Ref. Input Pairs Clock Outputs ispClock5510 1 10 ispClock5520 2 20 Figure 1. ispClock5510 Functional Block Diagram PS0 PS1 LOCK RESET PLL BYPASS SGATE GOE OEX OEY Profile Select Control OUTPUT ENABLE CONTROLS 0123 LOCK OUTPUT ROUTING DETECT SKEW OUTPUT MATRIX CONTROL DRIVERS OUTPUT BANK 0A DIVIDERS BANK 0B V0 (2-64) BANK 1A BANK 1B INPUT V1 DIVIDER (2-64) BANK 2A M REFA+ 1 BANK 2B V2 REFA- (1-32) PHASE LOOP (2-64) 0 VCO BANK 3A DETECT FILTER REFVTT BANK 3B V3 (2-64) BANK 4A BANK 4B FEEDBACK V4 N DIVIDER (2-64) (1-32) FEEDBACK SKEW ADJUST JTAG INTERFACE TDI TMS TCK TDO 2