ispClock 5600A Family In-System Programmable, Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer June 2008 Data Sheet DS1019 Up to Five Clock Frequency Domains Features Flexible Clock Reference and External 8MHz to 400MHz Input/Output Operation Feedback Inputs Low Output to Output Skew (<50ps) Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, Low Jitter Peak-to-Peak LVPECL, Differential HSTL, SSTL Up to 20 Programmable Fan-out Buffers Clock A/B selection multiplexer Programmable output standards and individual Feedback A/B selection multiplexer enable controls Programmable termination - LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL All Inputs and Outputs are Hot Socket Programmable output impedance Compliant - 40 to 70 in 5 increments Four User-programmable Proles Stored in 2 Programmable slew rate E CMOS Memory Up to 10 banks with individual V and GND CCO Supports both test and multiple operating - 1.5V, 1.8V, 2.5V, 3.3V congurations Fully Integrated High-Performance PLL Full JTAG Boundary Scan Test In-System Programmable lock detect Programming Support Multiply and divide ratio controlled by Exceptional Power Supply Noise Immunity - Input divider (1 to 40) Commercial (0 to 70C) and Industrial - Feedback divider (1 to 40) (-40 to 85C) Temperature Ranges - Five output dividers (2 to 80) 100-pin and 48-pin TQFP Packages Programmable on-chip loop lter Compatible with spread spectrum clocks Applications Circuit board common clock generation and Precision Programmable Phase Adjustment distribution (Skew) Per Output PLL-based frequency generation 16 settings minimum step size 156ps High fan-out clock buffer - Locked to VCO frequency Zero-delay clock buffer Up to +/- 12ns skew range Coarse and ne adjustment modes Product Family Block Diagram LOCK DETECT OUTPUT DIVIDERS SKEW OUTPUT V0 CONTROL DRIVERS BYPASS MUX V1 M * V2 PHASE/ FREQUENCY FILTER VCO DETECTOR V3 N OUTPUT V4 ROUTING PLL CORE MATRIX Internal/External JTAG Feedback Multiple Profile INTERFACE Select Management Logic & 2 E CMOS 021 3 * MEMORY INTERNAL FEEDBACK PATH * Input Available only on ispClock5620A 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1019 01.4 FEEDBACK REFERENCE INPUTS INPUTS CLOCK OUTPUTS Lattice Semiconductor ispClock5600A Family Data Sheet General Description and Overview The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock gen- erators designed for use in high performance communications and computing applications. The ispClock5610A provides up to 10 single-ended or ve differential clock outputs, while the ispClock5620A provides up to 20 single- ended or 10 differential clock outputs. Each pair of outputs may be independently congured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent programmable control of termination, slew-rate, and timing skew. All conguration informa- 2 tion is stored on-chip in non-volatile E CMOS memory. The ispClock5600As PLL and divider systems supports the synthesis of multiple clock frequencies derived from the reference input through the provision of programmable input and feedback dividers. A set of ve post-PLL V- dividers provides additional exibility by supporting the generation of ve separate output frequencies. Loop feed- back may be taken internally from the output of any of the ve V-dividers, or externally through FBKA+/- or FBKB+/- pins. The core functions of all members of the ispClock5600A family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ispClock5610A and ispClock5620A. Table 1-1. ispClock5600A Family Members Device Ref. Input Pairs Feedback Input Pairs Clock Outputs ispClock5610A 1 1 10 ispClock5620A 2 2 20 Figure 1-1. ispClock5610A Functional Block Diagram PS0 PS1 LOCK RESET PLL BYPASS SGATE GOE OEX OEY Profile Select Control OUTPUT ENABLE CONTROLS 01 2 3 LOCK OUTPUT ROUTING SKEW OUTPUT DETECT MATRIX CONTROL DRIVERS OUTPUT BANK 0 DIVIDERS BANK 0 V0 (2-80) BANK 1 BANK 1 INPUT V1 (2-80) DIVIDER BANK 2 M REFA+ 1 BANK 2 V2 REFA- (1-40) PHASE LOOP (2-80) VCO 0 BANK 3 DETECT FILTER REFVTT BANK 3 V3 (2-80) BANK 4 FEEDBACK BANK 4 N V4 (1-40) DIVIDER (2-80) FEEDBACK 2 E Configuration SKEW ADJUST FBKA+ FBKA - FBKVTT JTAG INTERFACE TDI TMS TCK TDO 1-2