ORCA ORSO42G5 and ORSO82G5 0.6 - 2.7 Gbps SONET Backplane Interface FPSCs August 2005 Data Sheet Introduction Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5 devices. Built on the Series 4 recongurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbits/s and 20 Gbits/s respectively. These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non- SONET applications. The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6- 2.7Gbits/s SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable FPGA system gates. The CDR circuitry, available from Lattices high-speed I/O portfolio (sysHSI), has already been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces. With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design- ers can build a congurable interface using proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbits/s backplane data connection and, with the ORSO82G5, support both work and protection connections between a line card and switch fabric. The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network designers will benet from using the backplane transceiver as a network termination device. Sister devices, the ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet (XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling, streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi- nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices. Table 1. ORCA ORSO42G5 and ORSO82G5 Family Available FPGA Logic FPGA PFU FPGA Max EBR EBR Bits System 2 1 Device PFU Rows Columns Total PFUs User I/O LUTs Blocks (K) Gates (K) ORSO42G5 36 36 1296 204 10,368 12 111 333-643 ORSO82G5 36 36 1296 372 10,368 12 111 333-643 1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 4 PLLs. 2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 orsox2g5 06.0 Lattice Semiconductor ORCA ORSO42G5 and ORSO82G5 Data Sheet Sample Initialization Sequences ORSO82G5.........70 Table of Contents Reset Conditions........................................................72 Introduction .................................................................. 1 SERDES Characterization Test Mode Table of Contents......................................................... 2 (ORSO82G5 Only)...............................................73 Embedded Function Features...................................... 3 Embedded Core Block RAM ......................................74 Programmable Features .............................................. 4 Register Maps ............................................................76 Programmable Logic System Features........................ 5 Types of Registers ........................................77 Description ................................................................... 6 Absolute Maximum Ratings .....................................108 What Is an FPSC .......................................... 6 Recommended Operating Conditions......................108 FPSC Overview............................................... 6 SERDES Electrical and Timing Characteristics .......108 FPSC Gate Counting ...................................... 6 High Speed Data Transmitter......................109 FPGA/Embedded Core Interface .................... 6 High Speed Data Receiver..........................110 ispLEVER Development System..................... 7 External Reference Clock ...........................112 FPSC Design Kit ............................................. 7 Pin Descriptions .......................................................113 ORSO82G5/42G5 FPGA Logic Overview....... 7 Power Supplies ........................................................118 ORCA Series 4 FPGA Logic Overview ........... 7 Power Supply Descriptions .........................118 PLC Logic........................................................ 8 Recommended Power Supply Programmable I/O........................................... 8 Connections..........................................118 Routing............................................................ 9 Recommended Power Supply Filtering System Level Features ................................... 9 Scheme.................................................118 MicroProcessor Interface ................................ 9 Package Information ................................................120 System Bus..................................................... 9 Package Pinouts .........................................120 Phase-Locked Loops ...................................... 9 Package Thermal Characteristics Summary............148 Embedded Block RAM.................................. 10 ..............................................................148 JA Configuration................................................. 10 ..............................................................148 JC ORSO42G5 and ORSO82G5 Overview .................... 10 ..............................................................148 JC Embedded Core Overview............................ 11 ..............................................................148 JB ORSO42G5 and ORSO82G5 Main FPSC Maximum Junction Temperature ......149 Operating Modes - Overview.................. 12 Package Thermal Characteristics ...............149 Embedded Core Functional Blocks - Heat Sink Vendors for BGA Packages........149 Overview................................................. 13 Package Parasitics......................................149 Loopback - Overview .................................... 14 Package Outline Drawings..........................150 FPSC Configuration - Overview.................... 15 Part Number Description..........................................151 ORSO42G5 and ORSO82G5 Embedded Core Device Type Options...................................151 Detailed Description ............................................ 16 Ordering Information ................................................151 Top Level Description - Transmitter (TX) Conventional Packaging .............................151 and Receiver (RX) Architectures ............ 16 Lead-Free Packaging..................................152 Detailed Description - SERDES Only Mode....................................................... 19 32:8 MUX ...................................................... 21 SONET Mode Operation Detailed Description ............................... 24 SONET Mode Transmit Path ........................ 30 SONET Mode Receive Path ......................... 33 Cell Mode Detailed Description..................... 49 Cell Mode Transmit Path............................... 52 Cell Mode Receive Path................................ 56 Cell Extractor................................................. 56 Receive FIFO................................................ 57 Input Port Controllers .................................... 57 IPC Receive Cell Mode Timing Core/FPGA ............................................. 59 Reference Clock Requirements .................... 67 Sample Initialization Sequences ORSO42G5......... 69 2