ORCA ORT42G5 and ORT82G5 06 to 3.7 Gbits/s XAUI and FC FPSCs August 2005 Data Sheet Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 recongurable embedded System-on-a-Chip (SoC) architecture, the ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively. Each channel operates at up to 3.7 Gbits/s across 26 inches of FR-4 backplane, with a full-duplex synchronous interface with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K usable FPGA system gates. The CDR circuitry available from Lattices high-speed I/O portfolio (sysHSI), has already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet (GbE, 10 GbE) applications. Designers can also use these devices to drive high-speed data transfer across buses within any generic system. For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a XAUI interface with a congurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and protection links between a line card and switch fabric. The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system perfor- mance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benet from the backplane transceiver as a network termination device. The device supports embed- ded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel. The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5, which implements four channels of SERDES with SONET scrambling and cell processing. Table 1. ORCA ORT42G5 and ORT82G5 Family Available FPGA Logic 2 PFU FPGA Max. EBR EBR Bits FPGA System 2 1 Device PFU Rows Columns Total PFUs User I/O LUTs Blocks (K) Gates (K) ORT42G5 36 36 1296 204 10,368 12 111 333-643 ORT82G5 36 36 1296 372 10,368 12 111 333-643 1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and four PLLs. 2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic. 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 42g582g5 05.0 Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet Reference Clock Requirements ....................37 Table of Contents Synthesized and Recovered Clocks .............37 Introduction .................................................................. 1 Internal Clock Signals at the FPGA/Core Interface Table of Contents......................................................... 2 for the ORT42G5 .................................................38 Embedded Function Features...................................... 4 Transmit and Receive Clock Rates...............39 Programmable Features .............................................. 5 Transmit Clock Source Selection ..................39 Programmable Logic System Features........................ 6 Recommended Transmit Clock Distribution Description ................................................................... 7 for the ORT42G5 ....................................39 What is an FPSC ........................................... 7 Multi-Channel Alignment Clocking FPSC Overview............................................... 7 Strategies for the ORT42G5...................41 FPSC Gate Counting ...................................... 7 Internal Clock Signals at the FPGA/Core Interface FPGA/Embedded Core Interface .................... 7 for the ORT82G5 .................................................43 FPSC Design Kit ............................................. 7 Transmit and Receive Clock Rates...............44 FPGA Logic Overview..................................... 8 Transmit Clock Source Selection ..................44 PLC Logic........................................................ 8 Recommended Transmit Clock Distribution Programmable I/O........................................... 8 for the ORT82G5 ....................................45 Routing............................................................ 9 Multi-Channel Alignment Clocking System-Level Features ................................................ 9 Strategies for the ORT82G5...................47 Microprocessor Interface................................. 9 Reset Operation.........................................................49 System Bus................................................... 10 Start Up Sequence for the ORT42G5 ...........50 Phase-Locked Loops .................................... 10 Start Up Sequence for the ORT82G5 ...........51 Embedded Block RAM.................................. 10 Test Modes ................................................................52 Configuration................................................. 10 Loopback Testing..........................................52 Additional Information ................................... 11 High-Speed Serial Loopback at the CML ORT42G5/ORT82G5 Overview ................................. 11 Buffer Interface .......................................53 Embedded Core Overview............................ 11 Parallel Loopback at the SERDES Serializer and Deserializer (SERDES).......... 11 Boundary ................................................54 MUX/DEMUX Block ...................................... 12 Parallel Loopback at MUX/DEMUX Multi-channel Alignment FIFOs..................... 12 Boundary, Excluding SERDES...............55 XAUI and Fibre Channel Link State SERDES Characterization Test Mode Machines....................................................... 12 (ORT82G5 Only).....................................55 FPGA/Embedded Core Interface .................. 12 Embedded Core Block RAM ......................................56 Dual Port RAMs ............................................ 13 Memory Maps ............................................................59 FPSC Configuration ...................................... 13 Definition of Register Types ..........................59 Backplane Transceiver Core Detailed Description .... 13 ORT42G5 Memory Map................................59 8b/10b Encoding and Decoding.................... 14 ORT82G5 Memory Map................................67 Transmit Path (FPGA to Backplane) Logic ... 16 Recommended Board-level Clocking for 8b/10b Encoder and 1:10 Multiplexer ........... 18 the ORT42G5 and ORT82G5.................73 CML Output Buffer ........................................ 18 Absolute Maximum Ratings .......................................75 Receive Path (Backplane to FPGA) Logic .... 19 Recommended Operating Conditions........................75 Link State Machines...................................... 24 SERDES Electrical and Timing Characteristics .........75 XAUI Link Synchronization Function............. 25 High Speed Data Transmitter........................76 Multi-channel Alignment............................................. 27 High Speed Data Receiver............................77 ORT42G5 Multi-channel Alignment .............. 27 External Reference Clock .............................79 ORT82G5 Multi-channel Alignment .............. 28 Embedded Core Timing Characteristics .......79 XAUI Lane Alignment Function Pin Descriptions .........................................................80 (Lane Deskew) ....................................... 29 Power Supplies for ORT42G5 AND ORT82G5..........85 Mixing Half-rate, Full-rate Modes.................. 30 Power Supply Descriptions ...........................85 Multi-channel Alignment Configuration ...................... 30 Recommended Power Supply ORT42G5 Configuration ............................... 30 Connections............................................85 ORT82G5 Configuration ............................... 31 Recommended Power Supply Filtering ORT42G5 Alignment Sequence.................... 32 Scheme...................................................85 ORT82G5 Alignment Sequence.................... 33 Package Information ..................................................87 Reference Clocks and Internal Clock Distribution...... 37 Package Pinouts ...........................................87 2