ORCA ORT8850 Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver February 2008 Data Sheet Introduction Field Programmable System-on-a-Chip (FPSCs) bring a whole new dimension to programmable logic: Field Pro- grammable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high- speed serial backplane data transfer. Built on the Series 4 recongurable embedded System-on-a-Chip (SoC) architecture, the ORT8850 family is made up of backplane transceivers (SERDES) containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used). This is combined with a full-duplex synchronous interface, with built-in Clock and Data Recovery (CDR) in standard-cell logic, along with over 600K usable FPGA system gates (ORT8850H). With the addition of protocol and access logic such as protocol-indepen- dent framers, Asynchronous Transfer Mode (ATM) framers, Packet-over-SONET (PoS) interfaces, and framers for HDLC for Internet Protocol (IP), designers can build a congurable interface retaining proven backplane driver/receiver technology. Designers can also use the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. For example, designers can build a 6.8 Gbits/s PCI-to-PCI half bridge using our PCI soft core. The ORT8850 family offers a clockless High-Speed Interface for inter-device communication on a board or across a backplane. The built-in clock recovery of the ORT8850 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benet from the backplane transceiver as a network termination device. The backplane transceiver offers SONET scram- bling/descrambling of data and streamlined SONET framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. For non-SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. Table 1. ORCA ORT8850 Family Available FPGA Logic (equivalent to OR4E02 and OR4E06 respectively) FPGA PFU FPGA Max EBR EBR Bits System Device PFU Rows Columns Total PFUs User I/Os LUTs Blocks (K) Gates (K) ORT8850L 26 24 624 278 4,992 8 74 201 - 397 ORT8850H 46 44 2,024 297 16,192 16 148 471 - 899 Note: The embedded core, embedded system bus, FPGA interface and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLL s. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs. 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1 ort8850 11.1 Lattice Semiconductor ORCA ORT8850 Data Sheet Package Thermal Characteristics Summary............100 Table of Contents qJA ..............................................................100 Introduction .................................................................. 1 YJC .............................................................100 Table of Contents......................................................... 2 qJC..............................................................100 Features....................................................................... 3 qJB ..............................................................100 Embedded Core Features............................... 3 FPSC Maximum Junction Temperature ......101 FPGA Features ............................................... 4 Package Thermal Characteristics ...............101 Programmable Logic System Features........... 5 Heat Sink Information..................................101 Description ................................................................... 6 Package Coplanarity ...................................101 What is an FPSC ........................................... 6 Package Parasitics...................................................102 FPSC Overview............................................... 6 Package Outline Diagrams ......................................102 ispLEVER Development System..................... 7 Terms and Definitions .................................102 FPSC Design Kit ............................................. 7 Package Outline Drawings..........................103 FPGA Logic Overview..................................... 8 Ordering Information ................................................104 System-Level Features ................................... 9 Revision History .......................................................105 Configuration................................................. 10 Additional Information ................................... 10 ORT8850 Overview ................................................... 11 Embedded Core Overview............................ 11 SONET Logic Blocks - Overview .................. 12 System Considerations for Reference Clock Distribution.............................................. 15 SONET Bypass Mode................................... 16 STM Macrocells - Overview .......................... 17 HSI Macrocell - Overview.............................. 19 Supervisory and Test Support Features - Over- view ........................................................ 19 Protection Switching - Overview ................... 21 FPSC Configuration - Overview.................... 22 Backplane Transceiver Core Detailed Description .... 25 SONET Logic Blocks, Detailed Description .. 25 Receive Path Logic ....................................... 34 FPGA/Embedded Core Interface Signals .................. 47 Clock and Data Timing at the FPGA/Embedded Core Interface - SONET Block ............... 49 Powerdown Mode ......................................... 56 Protection Switching...................................... 56 Memory Map .............................................................. 57 Registers Access and General Description... 57 Electrical Characteristics............................................ 69 Absolute Maximum Ratings .......................... 69 Recommended Operating Conditions........................ 69 Power Supply Decoupling LC Circuit ............ 70 HSI Electrical and Timing Characteristics..... 71 Embedded Core LVDS I/O............................ 73 Pin Information........................................................... 77 Package Pinouts ........................................................ 82 2