ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO JUNE 2006 REV. 4.0.1 FEATURES GENERAL DESCRIPTION Pin-to-pin compatible with the industry standard The ST16C554/554D (554) is a quad Universal ST16C454, ST68C454, ST68C554, TIs Asynchronous Receiver and Transmitter (UART) with TL16C554A and Philips SC16C554B 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates of up to 1.5 Intel or Motorola Data Bus Interface select Mbps. Each UART has a set of registers that provide Four independent UART channels the user with operating status and control, receiver error indications, and modem serial interface Register Set Compatible to 16C550 controls. An internal loopback capability allows Data rates of up to 1.5 Mbps at 5 V onboard diagnostics. The 554 is available in a 64-pin Data rates of up to 500 Kbps at 3.3V LQFP and a 68-pin PLCC package. The 64-pin 16 byte Transmit FIFO package only offers the 16 mode interface, but the 68-pin package offers an additional 68 mode 16 byte Receive FIFO with error tags interface which allows easy integration with Motorola 4 Selectable RX FIFO Trigger Levels processors. The ST16C554CQ64 (64-pin) offers Full modem interface three state interrupt output while the ST16C554DCQ64 provides continuous interrupt 2.97V to 5.5V supply operation output. The 554 combines the package interface Crystal oscillator or external clock input modes of the 16C554 and 68C554 on a single integrated chip. APPLICATIONS Portable Appliances Telecommunication Network Routers Ethernet Network Routers Cellular Data Devices Factory Automation and Process Controls FIGURE 1. ST16C554 BLOCK DIAGRAM 2.97 V to 5.5 V VCC A2:A0 GND D7:D0 UART Channel A IOR 16 Byte TX FIFO UART TXA, RXA, IRTXA, DTRA , IOW Regs IR DSRA , RTSA , CTSA , TX & RX CSA ENDEC CDA , RIA BRG CSB 16 Byte RX FIFO CSC TXB, RXB, IRTXB, DTRB , CSD UART Channel B DSRB , RTSB , CTSB , (same as Channel A) INTA Data Bus CDB , RIB Interface INTB INTC TXC, RXC, IRTXC, DTRC , UART Channel C DSRC , RTSC , CTSC , (same as Channel A) INTD CDC , RIC TXRDY A-D TXD, RXD, IRTXD, DTRD , UART Channel D RXRDY A-D DSRD , RTSD , CTSD , (same as Channel A) Reset CDD , RID 16 68 / XTAL1 Crystal Osc Buffer INTSEL / XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO REV. 4.0.1 FIGURE 2. PIN OUT ASSIGNMENT DSRA 10 60 DSRD DSRA 10 60 DSRD CTSA 11 59 CTSD CTSA 11 59 CTSD DTRA 12 58 DTRD DTRA 12 58 DTRD VCC 13 57 GND VCC 13 57 GND 14 RTSA 56 RTSD RTSA 14 56 RTSD IRQ 15 55 N.C. INTA 15 55 INTD CS 16 54 N.C. CSA 16 54 CSD ST16C554 ST16C554 TXA 17 53 TXD TXA 17 53 TXD 68-pin PLCC 68-pin PLCC R/W 18 52 N.C. IOW 18 52 IOR Motorola Mode Intel Mode TXB 19 51 TXC 19 TXB 51 TXC (16/68 pin connected to GND) (16/68 pin connected to VCC) A3 20 50 A4 20 50 CSB CSC N.C. 21 49 N.C. INTB 21 49 INTC RTSB 22 48 RTSC RTSB 22 48 RTSC GND 23 47 VCC GND 23 47 VCC DTRB 24 46 DTRC DTRB 24 46 DTRC 25 45 CTSB 25 45 CTSC CTSB CTSC DSRB 26 44 DSRC DSRB 26 44 DSRC DSRA 10 60 DSRD DSRA 1 48 DSRD CTSA 11 59 CTSD CTSA 2 47 CTSD DTRA 12 58 DTRD DTRA 3 46 DTRD VCC 13 57 GND VCC 4 45 GND RTSA 14 56 RTSD RTSA 5 44 RTSD IRQ 15 55 N.C. INTA 6 43 INTD CSA 7 42 CSD CS 16 54 N.C. ST16C554/554D ST68C554 TXA 8 41 TXD TXA 17 53 TXD 64-pin TQFP 68-pin PLCC IOW 9 40 IOR R/W 18 52 N.C. Intel Mode Only Motorola Mode Only TXB 10 39 TXC 19 TXB 51 TXC CSB 11 38 CSC A3 20 50 A4 INTB 12 37 INTC N.C. 21 49 N.C. RTSB 13 36 RTSC RTSB 22 48 RTSC 14 35 VCC GND GND 23 47 VCC DTRB 15 34 DTRC DTRB 24 46 DTRC CTSB 16 33 CTSC CTSB 25 45 CTSC DSRB 26 44 DSRC ORDERING INFORMATION OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS RANGE ST16C554CQ64 64-Lead LQFP 0C to +70C Active ST16C554DCQ64 64-Lead LQFP 0C to +70C Active ST16C554DIQ64 64-Lead LQFP -40C to +85C Active ST16C554DCJ68 68-Lead PLCC 0C to +70C Active ST16C554DIJ68 68-Lead PLCC -40C to +85C Active ST68C554CJ68 68-Lead PLCC 0C to +70C Active ST68C554IJ68 68-Lead PLCC -40C to +85C Active 2 CDB 27 9 CDA CDA DSRB 17 64 RIB 28 8 RIA CDB 18 63 RIA RXB 29 7 RXA RXA RIB 19 62 VCC 30 6 GND RXB 20 61 GND 16/68 31 5 D7 VCC 21 60 D7 A2 32 4 D6 A2 59 D6 22 A1 33 3 D5 A1 23 58 D5 A0 34 2 D4 A0 24 57 D4 XTAL1 35 1 D3 XTAL1 25 56 D3 XTAL2 36 68 D2 XTAL2 26 55 D2 RESET 37 67 D1 RESET 27 54 D1 RXRDY 38 66 D0 GND 28 53 D0 TXRDY 39 65 INTSEL RXC 29 52 VCC GND 40 64 VCC RIC 30 51 RXD RXC 41 63 RXD CDC 31 50 RID RIC 42 62 RID CDD DSRC 32 49 CDC 43 63 CDD CDB 27 9 CDA CDB 27 9 CDA RIB 28 8 RIA RIB 28 8 RIA RXB 29 7 RXA RXB 29 7 RXA VCC 30 6 GND VCC 30 6 GND D7 GND 31 5 D7 16/68 31 5 A2 32 4 D6 A2 32 4 D6 A1 33 3 D5 A1 33 3 D5 A0 34 2 D4 A0 34 2 D4 XTAL1 35 1 D3 XTAL1 35 1 D3 XTAL2 36 68 D2 XTAL2 36 68 D2 RESET 37 67 D1 RESET 37 67 D1 RXRDY 38 66 D0 RXRDY 38 66 D0 GND TXRDY 39 65 GND TXRDY 39 65 VCC GND 40 64 VCC GND 40 64 RXC 41 63 RXD RXC 41 63 RXD RIC 42 62 RID RIC 42 62 RID CDC 43 63 CDD CDC 43 63 CDD