XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE AUGUST 2009 REV. 1.0.1 FEATURES GENERAL DESCRIPTION VLIO bus interface 1 The XR16M681 (M681) is an enhanced Universal Asynchronous Receiver and Transmitter (UART) with Pin-to-pin compatible with SC16C850V and a VLIO bus interface and has 32 bytes of transmit SC16C850SV in 32-QFN package and receive FIFOs, programmable transmit and 20 Mbps maximum data rate receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 20 Mbps Programmable TX/RX FIFO Trigger Levels at 3.3V, 16 Mbps at 2.5V and 10 Mbps at 1.8V with TX/RX FIFO Level Counters 4X data sampling rate. Independent TX/RX Baud Rate Generator The Auto RS-485 Half-Duplex Direction control feature simplifies both the hardware and software for Fractional Baud Rate Generator half-duplex RS-485 applications. In addition, the Auto RTS/CTS Hardware Flow Control Multidrop mode with Auto Address detection increases the performance by simplifying the Auto XON/XOFF Software Flow Control software routines. Auto RS-485 Half-Duplex Direction Control The Independent TX/RX Baud Rate Generator Multidrop mode w/ Auto Address Detect feature allows the transmitter and receiver to operate at different baud rates. Power consumption of the Sleep Mode with Automatic Wake-up M681 can be minmized by enabling the sleep mode PowerSave mode and PowerSave mode. Infrared (IrDA 1.0 and 1.1) mode The M681 has a 16550 compatible register set that provide users with operating status and control, 1.62V to 3.63V supply operation receiver error indications, and modem serial interface Crystal oscillator or external clock input controls. An internal loopback capability allows onboard diagnostics. The M681 is available in 24-pin APPLICATIONS QFN, 32-pin QFN and 25-pin BGA packages. Personal Digital Assistants (PDA) NOTE: 1 Covered by U.S. Patent 5,649,122. Cellular Phones/Data Devices Battery-Operated Devices Global Positioning System (GPS) Bluetooth FIGURE 1. XR16M681 BLOCK DIAGRAM VCC PwrSave (1.62 to 3.63 V) LLA GND AD7:AD0 TX 32 Byte TX FIFO IOR BRG TX, RX, IOW UART RTS , CTS , CS IR TX & DTR , DSR , ENDEC Regs RX RI , CD INT VLIO Bus Interface RX RESET 32 Byte RX FIFO BRG XTAL1 Crystal Osc/Buffer XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE REV. 1.0.1 FIGURE 2. PIN OUT ASSIGNMENT 24 23 22 21 20 19 18 17 18 17 16 15 14 13 VCC 19 12 IOR NC DSR 25 16 CD AD0 20 11 GND 26 15 NC RI 14 IOR 27 AD1 21 10 IOW 24-pin QFN VCC 32-pin QFN 28 13 GND AD2 22 9 XTAL2 AD0 29 12 IOW 23 8 AD3 XTAL1 30 AD1 XTAL2 11 24 7 31 AD4 PWRSAVE AD2 XTAL1 10 123 456 AD3 32 9 PWRSAVE 23 4 5 6 78 1 A1 Corner 1 2 3 4 5 A B C D E Transparent Top View CTS RESET RTS LLA IOR VCC AD5 DTR INT GND AD0 AD7 RX DSR XTAL2 AD3 AD1 CS PWRSAVE XTAL1 AD4 AD2 AD6 TX IOW ORDERING INFORMATION OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS RANGE XR16M681IL24 24-Pin QFN -40C to +85C Active XR16M681IL32 32-Pin QFN -40C to +85C Active XR16M681IB25 25-Pin BGA -40C to +85C Active 2 CTS AD5 RESET AD6 RTS AD7 INT RX LLA TX NC CS AD4 CTS NC RESET AD5 DTR AD6 RTS AD7 INT RX LLA TX NC CS NC