XRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MAY 2004 REV. 1.0.0 XRT83SL34 provides a variety of loop-back and GENERAL DESCRIPTION diagnostic features as well as transmit driver short The XRT83SL34 is a fully integrated Quad (four circuit detection and receive loss of signal monitoring. channel) short-haul line interface unit for T1 It supports internal impedance matching for 75, (1.544Mbps) 100, E1 (2.048Mbps) 75 or 120, or 100, 110 and 120 for both transmitter and J1 110 applications. receiver. In the absence of the power supply, the In T1 applications, the XRT83SL34 can generate five transmit outputs and receive inputs are tri-stated transmit pulse shapes to meet the short-haul Digital allowing for redundancy applications The chip Cross-Connect (DSX-1) template requirements. It includes an integrated programmable clock multiplier also provides programmable transmit pulse that can synthesize T1 or E1 master clocks from a generators for each channel that can be used for variety of external clock sources. output pulse shaping allowing performance APPLICATIONS improvement over a wide variety of conditions. T1 Digital Cross-Connects (DSX-1) The XRT83SL34 provides both a parallel Host microprocessor interface as well as a Hardware ISDN Primary Rate Interface mode for programming and control. CSU/DSU E1/T1/J1 Interface Both the B8ZS and HDB3 encoding and decoding T1/E1/J1 LAN/WAN Routers functions are selectable as well as AMI. An on-chip Public switching Systems and PBX Interfaces crystal-less jitter attenuator with a 32 or 64 bit FIFO T1/E1/J1 Multiplexer and Channel Banks can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The Features (See Page 2) FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 LIU (HOST MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 TAOS One of four channels, CHANNEL n - (n= 0:3) DRIVE DMO n DFM ENABLE MONITOR TPOS n/TDATA n TTIP n QRSS HDB3/ TX FILTER TX/RX JITTER TIMING LINE TNEG n/CODES n PATTERN B8ZS & PULSE ATTENUATOR CONTROL DRIVER GENERATOR ENCODER SHAPER TCLK n TRING n LBO 3:0 TXON n LOCAL QRSS ENABLE ANALOG REMOTE DIGITAL LOOPBACK LOOPBACK LOOPBACK LOOPBACK QRSS ENABLE DETECTOR RCLK n HDB3/ TIMING & PEAK RTIP n TX/RX JITTER RX RNEG n/LCV n B8ZS DATA DET ECTOR ATTENUATOR EQUALIZER RRING n DECODER RECOVERY & SLICER RPOS n/RDATA n NETWORK LOS AIS LOOP NLCD ENABLE EQUALIZER DETECTOR DETECTOR DETECTOR CONTROL RLOS n TEST ICT HW/HOST PTS1 WR R/W PTS2 RD DS MICROPROCESSOR CONTROLLER D 7:0 ALE-AS CS PCLK RDY DTACK A 7:0 INT RESET Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com JA SELECTXRT83SL34 QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.0 FIGURE 2. BLOCK DIAGRAM OF THE XRT83SL34 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKOUT MASTER CLOCK SYNTHESIZER MCLKT1 CLKSEL 2:0 TAOS n One of four Channels, CHANNEL n - (n=0 : 3) DRIVE DFM DMO n MONITOR TPOS n/TDATA n TTIP n QRSS HDB3/ TX FILTER TX/RX JITTER TIMING LINE TNEG n/CODES n PATTERN B8ZS & PULSE ATTENUATOR CONTROL DRIVER GENERATOR ENCODER SHAPER TCLK n TRING n LBO 3:0 LOCAL TXON n QRSS ENABLE REMOTE DIGITAL ANALOG LOOPBACK LOOPBACK LOOPBACK LOOPBACK QRSS ENABLE DETECTOR RCLK n HDB3/ TIMING & PEAK RTIP n TX/RX JITTER RX B8ZS DATA DETECTOR RNEG n/LCV n ATTENUATOR EQUALIZER RRING n DECODER RECOVERY & SLICER RPOS n/RDATA n NETWORK LOOP1 n LOS AIS LOOP NLCD ENABLE LOOP0 n EQUALIZER DETECTOR DETECTOR DETECTOR CONTROL RLOS n TEST ICT HW /HOST GAUGE RESET TRATIO JASEL1 JASEL0 SR/DR EQC 4:0 RXTSEL HARWARE CONTROL TCLKE TXTSEL TERSELR RCLKE RXMUTE XRES0 RXRES1 ATAOS FEATURES On-chip digital clock recovery circuit for high input jitter tolerance Fully integrated eight channel short-haul transceiv- ers for E1,T1 or J1 applications Crystal-less digital jitter attenuator with 32-bit or 64- bit FIFO selectable either in transmit or receive path Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform High receiver interference immunity generator for transmit output pulse shaping for both On-chip transmit short-circuit protection and limit- T1 and E1 modes. ing, and driver fail monitor output (DMO) Selectable receiver sensitivity from 0 to 36dB cable Receive loss of signal (RLOS) output loss On-chip HDB3/B8ZS/AMI encoder/decoder func- Receive monitor mode handles 0 to 29dB resistive tions attenuation along with 0 to 6dB of cable attenuation QRSS pattern generator and detection for testing for E1 and 0 to 3dB of cable attenuation for T1 and monitoring modes Error and Bipolar Violation Insertion and Detection Supports 75 and 120 (E1), 100 (T1) and 110 Receiver Line Attenuation Indication Output in 1dB (J1) applications steps Internal and/or external impedance matching for Network Loop-Code Detection for automatic Loop- 75, 100, 110 and 120 Back Activation/Deactivation Tri-State transmit output and receive input capabil- Transmit All Ones (TAOS) and In-Band Network ity for redundancy applications Loop Up and Down code generators Provides High Impedance for Tx and Rx during Supports Local Analog, Remote, Digital and Dual power off Loop-Back Modes Transmit return loss meets or exceeds ETSI 300- Meets or exceeds T1 and E1 short-haul network 166 standard access specifications in ITU G.703, G.775, G.736 2 JA SELECT