XRT91L33 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT AUG 2008 REV. V1.0.0 FEATURES APPLICATIONS Performs clock and data recovery for selectable data of 622.08 Mbps (STS-12/STM-4) or 155.52 SONET/SDH-based Transmission Systems Mbps (STS-3/STM-1) NRZ data Add/Drop Multiplexers Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 Cross Connect Equipment SONET Jitter Tolerance specification, and GR-253 ATM and Multi-Service Switches, Routers and CORE, GR-253 ILR SONET Jitter specifications. Switch/Routers Lock output pin monitors data run length and DSLAMS frequency drift from reference clock SONET/SDH Test Equipment Data is resampled at the output DWDM Termination Equipment Active High Signal Detect (SIGD) LVPECL input Low jitter, high-speed outputs support LVPECL and low-power LVDS termination GENERAL DESCRIPTION 19.44 MHz reference frequency LVTTL input The XRT91L33 is a fully integrated multirate Clock Low power: 215 mW typical and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/ 3.3V power supply STM-1 applications. The device provides Clock and 20-pin TSSOP package Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the Requires one external capacitor incoming serial scrambled non-return to zero (NRZ) PLL bypass operation facilitates board debug data stream. Figure 1 shows the block diagram of process the XRT91L33. ESD greater than 2kV on all pins FIGURE 1. BLOCK DIAGRAM OF XRT91L33 STS12 MODE REFCK 19.44 MHz CAP+ PLL RX LOOP 1u F FILTER CAP+ TEST LVDS/LVPECL Differential Output Drivers RECVD- Receiver DATAOUT RXDIP RXDOP 0 RXDATAIN CDR RXDIN RXDON STS-12/3 1 Internal or External biasing 100R STM-4/1 RECVD- RXCLKOP termination Clock and Data CLKOUT Recovery RXCLKON LOCK LCKTOREFN MUTE RXDO SIGD Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT91L33 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0 CLOCK AND DATA RECOVERY OVERVIEW The clock and data recovery (CDR) unit accepts high speed NRZ serial data from the Differential receiver and generates a clock with a frequency equal to that of the incoming data. The CDR block uses a reference clock to train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock (based on the local reference) to the framer/mapper device. An LOS condition occurs when either SIGD or LCKTOREFN is low. In this case, the receive serial data output is forced to a logic zero state for the entire duration of the LOS condition. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When SIGD becomes active again, the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream. FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW) 1 VDDA VDDA 20 2 RXDIP VSSA 19 3 RXDIN CAP+ 18 4 VSSA CAP- 17 5 TEST 16 LOCK 6 STS12 MODE SIGD 15 7 REFCK RXDOP 14 8 LCKTOREFN RXDON 13 9 VSS RXCLKOP 12 10 VDD RXCLKON 11 TABLE 1: ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT91L33IG 20-pin TSSOP Package -40 C to +85 C XRT91L33IG-F 20-Pin TSSOP Lead-Free Package -40 C to +85 C 2